利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

777 条记录 (耗时 0.031 秒)

    Self-test circuit for memory integrated circuits
    1.
    发明授权
    Self-test circuit for memory integrated circuits 失效

    公开(公告)号：US5754486A

    公开(公告)日：1998-05-19

    申请号：US808391

    申请日：1997-02-28

    申请人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

    发明人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

    IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/10 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C29/00

    CPC分类号： G11C29/10 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401

    摘要： A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and in response to the sensed voltage differential drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. An isolation circuit is coupled between the pair of first and second complementary digit lines of the sense amplifier and a pair of first and second complementary digit lines associated with a column of memory cells. The isolation circuit is operable to couple the first complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells and the second complementary digit line of the sense amplifier to the secondary complementary digit line of the column of memory cells. A switch circuit is operable to couple the first complementary digit line of the sense amplifier to the second complementary digit line of the column of memory cells, and the second complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells. An equilibration circuit is coupled between the pair of complementary digit lines of the column of memory cells and is operable to equalize the voltage level on the digit lines to a predetermined level.

    Self-test circuit for memory integrated circuits
    2.
    发明授权
    Self-test circuit for memory integrated circuits 失效
    存储器集成电路自检电路

    公开(公告)号：US5982682A

    公开(公告)日：1999-11-09

    申请号：US41859

    申请日：1998-03-12

    申请人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

    发明人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

    IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/10 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C29/00

    CPC分类号： G11C29/10 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401

    摘要： A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and in response to the sensed voltage differential drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. An isolation circuit is coupled between the pair of first and second complementary digit lines of the sense amplifier and a pair of first and second complementary digit lines associated with a column of memory cells. The isolation circuit is operable to couple the first complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells and the second complementary digit line of the sense amplifier to the secondary complementary digit line of the column of memory cells. A switch circuit is operable to couple the first complementary digit line of the sense amplifier to the second complementary digit line of the column of memory cells, and the second complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells. An equilibration circuit is coupled between the pair of complementary digit lines of the column of memory cells and is operable to equalize the voltage level on the digit lines to a predetermined level.

    摘要翻译： 读出放大器将存储单元中的数据传感并存储在以行和列排列的存储单元阵列中。 感测放大器包括感测电路，该感测电路具有一对第一和第二互补数字线，其感测第一和第二互补数字线之间的电压差，并且响应于感测到的电压差将第一和第二互补数字线驱动到相应的电压电平 互补逻辑状态。 隔离电路耦合在读出放大器的一对第一和第二互补数字线之间，以及与一列存储器单元相关联的一对第一和第二互补数字线。 隔离电路可操作以将读出放大器的第一互补数字线耦合到存储器单元列的第一互补数字线和读出放大器的第二互补数字线到存储器单元列的次互补数字线 。 开关电路可操作以将读出放大器的第一互补数字线耦合到存储器单元列的第二互补数字线，并将读出放大器的第二互补数字线耦合到存储器列的第一互补数字线 细胞。 平衡电路耦合在存储器单元列的一对互补数字线之间，并且可操作以将数字线上的电压电平均衡到预定电平。

    System for stressing a memory integrated circuit die
    3.
    发明授权
    System for stressing a memory integrated circuit die 失效
    用于强调存储器集成电路管芯的系统

    公开(公告)号：US5898629A

    公开(公告)日：1999-04-27

    申请号：US915757

    申请日：1997-08-21

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/56

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Wafer level burn-in of memory integrated circuits
    4.
    发明授权
    Wafer level burn-in of memory integrated circuits 有权
    晶圆级老化内存集成电路

    公开(公告)号：US06233185B1

    公开(公告)日：2001-05-15

    申请号：US09257403

    申请日：1999-02-25

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C1300

    CPC分类号： G11C29/006 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/1202

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Test arrangement for memory devices using a dynamic row for creating test data
    5.
    发明授权
    Test arrangement for memory devices using a dynamic row for creating test data 失效
    使用动态行创建测试数据的内存设备的测试安排

    公开(公告)号：US6094734A

    公开(公告)日：2000-07-25

    申请号：US917020

    申请日：1997-08-22

    申请人： Ray Beffa ,  Eugene H. Cloud ,  Leland R. Nevill ,  Ken Waller ,  Warren M. Farnworth

    发明人： Ray Beffa ,  Eugene H. Cloud ,  Leland R. Nevill ,  Ken Waller ,  Warren M. Farnworth

    IPC分类号： G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

    摘要： A test arrangement for a memory device wherein the equilibration voltage DVC2 is adjusted up or down relative to a nominal value and coupled to one of the bitlines of the paired bitlines of the memory array, while the equilibrating circuit is held disabled, and then the sense amplifiers are used to pull the bitlines to logic 1 and logic 0 levels initializing the bitlines to test data. Appropriate word lines are fired to copy the test data to some or all of the other rows of the memory array, allowing memory tests to be conducted. In another embodiment, a fixed voltage is applied to one of the bitlines of individual bitlines pairs and the sense amplifiers are used to pull the paired bitlines to the correct voltage. In a further embodiment, fixed voltages Vcc and ground are applied to the bitlines of each bitline pair with the sense amplifier being held disabled. The test arrangement can be implemented as a self-test feature for the memory device.

    摘要翻译： 一种用于存储器件的测试装置，其中平衡电压DVC2相对于标称值被上调或下调并耦合到存储器阵列的成对位线的位线之一，而平衡电路被保持禁用，然后感测 放大器用于将位线拉到逻辑1和逻辑0电平初始化位线以测试数据。 触发适当的字线将测试数据复制到存储器阵列的其他行的一些或全部，以进行内存测试。 在另一个实施例中，将固定电压施加到单个位线对的位线之一，并且读出放大器用于将成对的位线拉到正确的电压。 在另一个实施例中，将固定电压Vcc和接地施加到每个位线对的位线，使读出放大器保持禁用。 测试装置可以作为存储器件的自检特征来实现。

    Test method and apparatus for writing a memory array with a reduced number of cycles
    6.
    发明授权
    Test method and apparatus for writing a memory array with a reduced number of cycles 失效
    用于以减少的周期数写入存储器阵列的测试方法和装置

    公开(公告)号：US6003149A

    公开(公告)日：1999-12-14

    申请号：US917215

    申请日：1997-08-22

    申请人： Leland R. Nevill ,  Ray Beffa ,  Ken Waller ,  Eugene H. Cloud ,  Warren M. Farnworth

    发明人： Leland R. Nevill ,  Ray Beffa ,  Ken Waller ,  Eugene H. Cloud ,  Warren M. Farnworth

    IPC分类号： G11C29/34 ,  G11C29/00

    CPC分类号： G11C29/34

    摘要： A method of testing a memory array is disclosed, the method comprising writing a test pattern to the memory array in as few as one or two RAS cycles by first activating the input/output data lines and then selectively activating multiple rows and columns. The method can be used with a variety of test environments. For example, the disclosed method may be implemented in testing using automated test equipment, and may also be incorporated in devices having built-in self-test circuitry. The disclosed method reduces the time required to test the memory array with minimal additional circuitry and no encroachment on valuable die real estate.

    摘要翻译： 公开了一种测试存储器阵列的方法，所述方法包括通过首先激活输入/输出数据线然后选择性地激活多个行和列来将测试图案写入至少一个或两个RAS周期中的存储器阵列。 该方法可用于各种测试环境。 例如，所公开的方法可以在使用自动测试设备的测试中实现，并且还可以并入具有内置自测电路的设备中。 所公开的方法减少了以最小的附加电路测试存储器阵列所需的时间，并且不侵占有价值的裸片的不动产。

    Method of stress testing memory integrated circuits
    7.
    发明授权
    Method of stress testing memory integrated circuits 失效
    记忆体集成电路应力测试方法

    公开(公告)号：US5852581A

    公开(公告)日：1998-12-22

    申请号：US663515

    申请日：1996-06-13

    申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/56

    摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

    摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
    9.
    发明授权
    Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
    用于从半导体晶片上的其它IC隔离短路集成电路（IC）的方法

    公开(公告)号：US07276926B2

    公开(公告)日：2007-10-02

    申请号：US11607267

    申请日：2006-12-01

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/26

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。