公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06437623B1

公开(公告)日：2002-08-20

申请号：US09782435

申请日：2001-02-13

申请人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： H03K3289

CPC分类号： H03K3/0375 ,  G01R31/319 ,  H03K3/35625

摘要： A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.

摘要翻译： 数据保留系统具有用于保持活动模式下的数据的主从锁存器; 数据保持锁存器，用于在休眠模式下保存从主锁存器读取的数据，其与从锁存器并行连接到主锁存器; 第一多路复用器，用于接收外部提供的数据并从数据保持锁存器反馈数据，并且响应于第一控制信号选择性地输出外部提供的数据或反馈数据到主锁存器; 以及第二多路复用器，用于响应于第二控制信号将主锁存器的输出数据传送到从锁存器和数据保持锁存器，其中数据保持锁存器的电源在睡眠模式下保持导通，而数据保持功率 系统除了数据保持锁存器被关闭。 数据保持锁存器可以包括由第二控制信号控制的栅极晶体管和具有用于保持通过栅极晶体管传送的数据的晶体管的数据保持单元，其中数据保持单元中的栅极晶体管和晶体管具有高阈值电压。

公开(公告)号：US06492227B1

公开(公告)日：2002-12-10

申请号：US09624563

申请日：2000-07-24

申请人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

发明人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

IPC分类号： H01L218234

CPC分类号： H01L21/28273

摘要： A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate. Support devices may be fabricated on the semiconductor substrate by a single damascene process this is integrated with the processes of fabricating the memory devices, so that top surfaces of the support devices and the memory devices are substantially coplanar.

摘要翻译： 提供了一种使用双镶嵌工艺在半导体衬底上制造存储器件的方法。 该方法包括以下步骤：在半导体衬底上形成用于至少一个存储器件的至少一个虚拟栅极结构，在至少一个虚拟栅极结构的周围沉积介电材料，蚀刻电介质材料和至少一个虚拟栅极结构 以形成至少一个控制栅极空隙和至少一个浮置栅极空隙，在所述至少一个浮置栅极空隙的底表面上形成栅极电介质层，在至少一个浮置栅极中的栅极介电层上沉积浮置栅极材料 空隙以形成浮置栅极，在浮置栅极上沉积介电层，以及将控制栅极材料沉积在所述至少一个控制栅极中的介电层上以形成控制栅极。 可以通过单个镶嵌工艺在半导体衬底上制造支撑装置，其与制造存储器件的工艺集成，使得支撑装置和存储装置的顶表面基本上共面。

公开(公告)号：US07447273B2

公开(公告)日：2008-11-04

申请号：US10708240

申请日：2004-02-18

申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H01L21/82 ,  H01P1/10

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

公开(公告)号：US07041525B2

公开(公告)日：2006-05-09

申请号：US10751205

申请日：2004-01-02

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L21/66 ,  H01L21/00

CPC分类号： H01L27/14634 ,  H01L27/1463 ,  H01L27/14643

摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

公开(公告)号：US06629291B1

公开(公告)日：2003-09-30

申请号：US09668977

申请日：2000-09-25

申请人： Russell J. Houghton ,  Joni C. Hsu ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Russell J. Houghton ,  Joni C. Hsu ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： G06F1750

CPC分类号： G06F1/28 ,  G06F17/5045 ,  G11C5/14

摘要： A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.

摘要翻译： 一种用于多系统片上设备的集中供电系统包括：用于向设备供电的外部电源; 集中式DC发电机宏，其具有用于接收所提供的外部电力并由其产生的一个或多个电源电压，用于由多系统芯片上提供的周围系统宏使用的发电机组件，集中式DC发电机宏进一步将生成的电源电压分配到 各自的系统宏。 提供了围绕集中式DC发电机系统的隔离结构，并将集中式DC发电机系统与周围系统宏隔离开来。

公开(公告)号：US06614714B2

公开(公告)日：2003-09-02

申请号：US10055149

申请日：2002-01-22

申请人： Louis L. Hsu ,  Jeremy K. Stephens ,  Daniel W. Storaska ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Jeremy K. Stephens ,  Daniel W. Storaska ,  Li-Kong Wang

IPC分类号： G11C818

CPC分类号： G11C7/222 ,  G11C7/1006 ,  G11C7/1072 ,  G11C2207/104

摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.

摘要翻译： 提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。 半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。 数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。 在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。 还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。 在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近， 至少一个时钟驱动器位于第二时钟路径的近端附近。

公开(公告)号：US06579743B2

公开(公告)日：2003-06-17

申请号：US10041639

申请日：2002-01-07

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

IPC分类号： H01L2100

CPC分类号： H01L23/473 ,  H01L23/3677 ,  H01L23/3732 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  Y10S257/93 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

公开(公告)号：US06400619B1

公开(公告)日：2002-06-04

申请号：US09841950

申请日：2001-04-25

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C2207/104

摘要： A new micro-cell redundancy scheme for a wide bandwidth embedded DRAM having a SRAM cache interface. For each bank of micro-cell array units comprising the eDRAM, at least one micro-cell unit is prepared as the redundancy to replace a defected micro-cell within the bank. After array testing, any defective micro-cell inside the bank is replaced with a redundancy micro-cell for that bank. A fuse bank structure implementing a look-up table is established for recording each redundant micro-cell address and its corresponding repaired micro-cell address. In order to allow simultaneous multi-bank operation, the redundant micro-cells may only replace the defective micro-cells within the same bank. When reading data from eDRAM, or writing data to eDRAM, the micro-cell array address is checked against the look-up table to determine whether that data is to be read from or written to the original micro-cell, or the redundant micro-cell. The micro-cell redundancy scheme is a flexible and reliable method for high-performance eDRAM applications.

摘要翻译： 一种用于具有SRAM缓存接口的宽带宽嵌入式DRAM的新型微小区冗余方案。 对于包括eDRAM的每个微单元阵列单元组，至少一个微单元单元被准备为冗余以替代该单元内的缺陷微单元。 在阵列测试之后，银行内的任何有缺陷的微单元被该银行的冗余微单元替代。 建立实现查找表的熔丝库结构，用于记录每个冗余微小区地址及其对应的修复的微小区地址。 为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。 当从eDRAM读取数据或将数据写入eDRAM时，将针对查找表检查微单元阵列地址，以确定该数据是从原始微单元读取还是写入原始微单元， 细胞。 微单元冗余方案是高性能eDRAM应用的灵活可靠的方法。

公开(公告)号：US06355531B1

公开(公告)日：2002-03-12

申请号：US09634225

申请日：2000-08-09

申请人： Jack A. Mandelman ,  Louis L. Hsu ,  Carl J. Radens ,  William R. Tonti ,  Li-Kong Wang

发明人： Jack A. Mandelman ,  Louis L. Hsu ,  Carl J. Radens ,  William R. Tonti ,  Li-Kong Wang

IPC分类号： H01L218236

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L21/82385 ,  Y10S438/981

摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.

摘要翻译： 提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。 该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得 第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第 除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层 在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。 半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。