公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06437623B1

公开(公告)日：2002-08-20

申请号：US09782435

申请日：2001-02-13

申请人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： H03K3289

CPC分类号： H03K3/0375 ,  G01R31/319 ,  H03K3/35625

摘要： A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.

摘要翻译： 数据保留系统具有用于保持活动模式下的数据的主从锁存器; 数据保持锁存器，用于在休眠模式下保存从主锁存器读取的数据，其与从锁存器并行连接到主锁存器; 第一多路复用器，用于接收外部提供的数据并从数据保持锁存器反馈数据，并且响应于第一控制信号选择性地输出外部提供的数据或反馈数据到主锁存器; 以及第二多路复用器，用于响应于第二控制信号将主锁存器的输出数据传送到从锁存器和数据保持锁存器，其中数据保持锁存器的电源在睡眠模式下保持导通，而数据保持功率 系统除了数据保持锁存器被关闭。 数据保持锁存器可以包括由第二控制信号控制的栅极晶体管和具有用于保持通过栅极晶体管传送的数据的晶体管的数据保持单元，其中数据保持单元中的栅极晶体管和晶体管具有高阈值电压。

公开(公告)号：US08587288B2

公开(公告)日：2013-11-19

申请号：US12823984

申请日：2010-06-25

申请人： Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

发明人： Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

IPC分类号： G01R31/3187

CPC分类号： G01R31/3004

摘要： A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of

摘要翻译： 提供了一种用于快速准确地统计表征CMOS工艺结构，MOS器件和电路参数的电气特性变化的电路架构和方法。 所提出的电路架构和方法使得在<2mV或<1nA分辨率的测试设备的电压或电流变化的分辨率精度下<1ms / DC扫描的统计特征吞吐量。 提出的电路架构的显着特征包括一个可激励被测器件的可编程斜坡电压发生器，一个双输入9-11位循环ADC，用于捕获输入和输出来自被测器件的直流电压/电流信号，一个2 Kb的锁存器 存储器，以可编程粒度的直流扫描为每个测量点捕获9-11位流，以及时钟和控制方案，其能够连续测量和流出数字数据块，从该模块重新测量被测器件的模拟特性 。

公开(公告)号：US08561004B2

公开(公告)日：2013-10-15

申请号：US12758525

申请日：2010-04-12

申请人： Stephen V. Kosonocky

发明人： Stephen V. Kosonocky

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： H01L27/0207 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.

摘要翻译： 功率门包括沿着集成电路的至少一部分的一系列电触点和电耦合到集成电路上的电触点的一系列功率栅极晶体管，以形成例如集成电路外围的功率门边界。 沿着电源栅极边界的运行长度的至少一部分的电触点限定了基本上非线性的轮廓。 非线性轮廓提供增加的接触密度，其改善电触头之间的电流平衡和通过功率门的电流吞吐量。 非线性轮廓是具有中间偏移碰撞触点的正弦曲线或锯齿形图案。 沿着功率门边界的接触曲线可以包括线性和非线性轮廓。

公开(公告)号：US20120126847A1

公开(公告)日：2012-05-24

申请号：US12950584

申请日：2010-11-19

申请人： Stephen V. Kosonocky ,  Gregory K. Chen

发明人： Stephen V. Kosonocky ,  Gregory K. Chen

IPC分类号： G01R31/40

CPC分类号： G01R31/40

摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

摘要翻译： 通过逐周期监测环形振荡器的性能来测量电源变化和抖动。 通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。 计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。 基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。

公开(公告)号：US07668035B2

公开(公告)日：2010-02-23

申请号：US12098764

申请日：2008-04-07

申请人： Sam Gat-Shang Chu ,  Saiful Islam ,  Jae-Joon Kim ,  Stephen V. Kosonocky

发明人： Sam Gat-Shang Chu ,  Saiful Islam ,  Jae-Joon Kim ,  Stephen V. Kosonocky

IPC分类号： G11C5/14

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/413 ,  G11C2207/2227

摘要： A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.

摘要翻译： 存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组 分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。 本地读位线与本地写位线分离。 本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线 。 全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。 还包括所述类型的电路的设计结构。

公开(公告)号：US20070300131A1

公开(公告)日：2007-12-27

申请号：US11446348

申请日：2006-06-02

申请人： Sam Gat-Shang Chu ,  Daniel R. Knebel ,  Stephen V. Kosonocky

发明人： Sam Gat-Shang Chu ,  Daniel R. Knebel ,  Stephen V. Kosonocky

IPC分类号： G11C29/00

CPC分类号： G11C29/52 ,  G11C29/32 ,  G11C2029/3202

摘要： Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.

摘要翻译： 为包括被配置为存储第一值的主存储部分和耦合到主存储部分的辅助存储部分的寄存器文件单元提供技术。 次存储部分被配置为在测试操作期间用作扫描锁存器，并且还被配置为在正常操作期间存储第二值。 第二个值是第一个值的副本。 小区还包括错误检测部分，其耦合到主存储部分和辅助存储部分，并且被配置为指示由软错误引起的第一值和第二值之间的差异。

公开(公告)号：US07259986B2

公开(公告)日：2007-08-21

申请号：US11089941

申请日：2005-03-25

申请人： Azeez J. Bhavnagarwala ,  Stephen V. Kosonocky

发明人： Azeez J. Bhavnagarwala ,  Stephen V. Kosonocky

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  G11C8/08

摘要： Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power supply and/or ground line voltages that are applied to the memory cells during different modes of memory operation to enable low voltage, high performance operation of the memory devices.

摘要翻译： 提供了电路和方法来实现诸如CMOS静态随机存取存储器（SRAM）或多端口寄存器文件的低电压，更高性能的半导体存储器件。 例如，电路和方法被提供用于在存储器操作的不同模式期间动态调整施加到存储器单元的电源和/或接地线电压，以实现存储器件的低电压，高性能的操作。

公开(公告)号：US07057180B2

公开(公告)日：2006-06-06

申请号：US10604416

申请日：2003-07-18

申请人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

发明人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

IPC分类号： G01T1/24

CPC分类号： G11C11/4125

摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。

公开(公告)号：US06891419B2

公开(公告)日：2005-05-10

申请号：US10604554

申请日：2003-07-30

申请人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

发明人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356104 ,  H03K3/0375

摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.

摘要翻译： 在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。 第二逆变器电路在多个节点处与第一反相器电路交叉耦合。 第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电 在交叉耦合的逆变器。