公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06437623B1

公开(公告)日：2002-08-20

申请号：US09782435

申请日：2001-02-13

申请人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： H03K3289

CPC分类号： H03K3/0375 ,  G01R31/319 ,  H03K3/35625

摘要： A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.

摘要翻译： 数据保留系统具有用于保持活动模式下的数据的主从锁存器; 数据保持锁存器，用于在休眠模式下保存从主锁存器读取的数据，其与从锁存器并行连接到主锁存器; 第一多路复用器，用于接收外部提供的数据并从数据保持锁存器反馈数据，并且响应于第一控制信号选择性地输出外部提供的数据或反馈数据到主锁存器; 以及第二多路复用器，用于响应于第二控制信号将主锁存器的输出数据传送到从锁存器和数据保持锁存器，其中数据保持锁存器的电源在睡眠模式下保持导通，而数据保持功率 系统除了数据保持锁存器被关闭。 数据保持锁存器可以包括由第二控制信号控制的栅极晶体管和具有用于保持通过栅极晶体管传送的数据的晶体管的数据保持单元，其中数据保持单元中的栅极晶体管和晶体管具有高阈值电压。

公开(公告)号：US06492227B1

公开(公告)日：2002-12-10

申请号：US09624563

申请日：2000-07-24

申请人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

发明人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

IPC分类号： H01L218234

CPC分类号： H01L21/28273

摘要： A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate. Support devices may be fabricated on the semiconductor substrate by a single damascene process this is integrated with the processes of fabricating the memory devices, so that top surfaces of the support devices and the memory devices are substantially coplanar.

摘要翻译： 提供了一种使用双镶嵌工艺在半导体衬底上制造存储器件的方法。 该方法包括以下步骤：在半导体衬底上形成用于至少一个存储器件的至少一个虚拟栅极结构，在至少一个虚拟栅极结构的周围沉积介电材料，蚀刻电介质材料和至少一个虚拟栅极结构 以形成至少一个控制栅极空隙和至少一个浮置栅极空隙，在所述至少一个浮置栅极空隙的底表面上形成栅极电介质层，在至少一个浮置栅极中的栅极介电层上沉积浮置栅极材料 空隙以形成浮置栅极，在浮置栅极上沉积介电层，以及将控制栅极材料沉积在所述至少一个控制栅极中的介电层上以形成控制栅极。 可以通过单个镶嵌工艺在半导体衬底上制造支撑装置，其与制造存储器件的工艺集成，使得支撑装置和存储装置的顶表面基本上共面。

公开(公告)号：US08487684B2

公开(公告)日：2013-07-16

申请号：US13155523

申请日：2011-06-08

申请人： Chung-Ying Hsieh ,  Ming-Hung Chang ,  Wei Hwang

发明人： Chung-Ying Hsieh ,  Ming-Hung Chang ,  Wei Hwang

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： G06F1/10

摘要： A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.

摘要翻译： 一种方法通过使用逻辑努力来缓冲时钟偏移，并且适用于停留在强反转区域，中等反转区域或弱反转区域中的时钟树。 该方法包括在时钟树中建立温度传感器和可调宽度缓冲器，并且根据逻辑努力方程建立宽度和温度比较列表，对于可单独应用于强反转区域的可调宽度缓冲器， 中等反演区域和弱反演区域; 从与时钟树停留的反转区域中的一个对应的宽度和温度比较列表中选择一个，使得温度传感器能够感测温度，并且在所选择的宽度和温度比较列表中搜索对应于温度的宽度 由温度传感器感测; 并且使得可调宽度缓冲器能够根据所搜索的宽度执行宽度调制处理。

公开(公告)号：US08419274B2

公开(公告)日：2013-04-16

申请号：US12910199

申请日：2010-10-22

申请人： Shi-Wen Chen ,  Ming-Hung Chang ,  Wei-Chih Hsieh ,  Wei Hwang

发明人： Shi-Wen Chen ,  Ming-Hung Chang ,  Wei-Chih Hsieh ,  Wei Hwang

IPC分类号： G01K7/00

CPC分类号： G01K7/01 ,  G01K2219/00

摘要： A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.

摘要翻译： 完全片上的温度，过程和电压传感器包括电压传感器，过程传感器和温度传感器。 温度传感器包括偏置电流发生器，环形振荡器，固定脉冲发生器，与门和第一计数器。 偏置电流发生器根据芯片的工作电压产生与温度相关的输出电流。 环形振荡器根据输出电流产生振荡信号。 固定脉冲发生器产生固定的脉冲信号。 与门连接到环形振荡器和固定脉冲发生器，用于对振荡信号和固定脉冲信号进行逻辑与运算，并产生温度传感器信号。

公开(公告)号：US08385149B2

公开(公告)日：2013-02-26

申请号：US13075682

申请日：2011-03-30

申请人： Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

发明人： Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

摘要翻译： 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US08345504B2

公开(公告)日：2013-01-01

申请号：US13009240

申请日：2011-01-19

申请人： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

发明人： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

IPC分类号： G11C11/40

CPC分类号： G11C11/413 ,  G11C11/412

摘要： A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

摘要翻译： 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

公开(公告)号：US20120230086A1

公开(公告)日：2012-09-13

申请号：US13096796

申请日：2011-04-28

申请人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

发明人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

摘要翻译： 静态随机存取存储单元包括一个锁存单元。 锁存单元包括双向电路和开关电路。 双向电路具有第一端子和第二端子。 开关电路电连接在第一端子和第二端子之间，其中当开关电路导通时，开关电路在第一端子和第二端子之间形成用于锁存闩锁单元的反馈; 并且当切换电路关闭时，消除反馈以使SRAM单元向锁存单元写入数据位。

公开(公告)号：US08237477B1

公开(公告)日：2012-08-07

申请号：US13067232

申请日：2011-05-18

申请人： Chung-Ying Hsieh ,  Ming-Hung Chang ,  Wei Hwang

发明人： Chung-Ying Hsieh ,  Ming-Hung Chang ,  Wei Hwang

IPC分类号： H03L7/06

CPC分类号： H03L7/0816 ,  H03L1/00 ,  H03L7/0814

摘要： A programmable clock generator, which is used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region. The programmable clock generator includes first pulse generating unit and a pulse multiplier. A first counter is configured to generate a first counting signal, so as to control the phase detector comparing the phase difference between a first pulse signal and a second pulse signal. A first control signal is transmitted by a control unit in accordance with a phase difference signal, and the phase of the second pulse signal is adjusted by a lock-in delay unit, so that a predetermined phase is generated between the first pulse signal and the second pulse signal. The PVT variation may be compensated by the programmable clock generator during the sub threshold region. Therefore, the period of reference clock is in the locking range of lock-in delay line.

摘要翻译： 可编程时钟发生器，用于在子阈值和近阈值区域工作的动态电压和频率缩放（DVFS）。 可编程时钟发生器包括第一脉冲发生单元和脉冲乘法器。 第一计数器被配置为产生第一计数信号，以便控制相位检测器比较第一脉冲信号和第二脉冲信号之间的相位差。 第一控制信号由控制单元根据相位差信号发送，第二脉冲信号的相位由锁定延迟单元调整，使得在第一脉冲信号和第二脉冲信号之间产生预定的相位 第二脉冲信号。 PVT变化可以由子阈值区域内的可编程时钟发生器补偿。 因此，参考时钟周期处于锁定延迟线的锁定范围。

公开(公告)号：US07738275B2

公开(公告)日：2010-06-15

申请号：US12007826

申请日：2008-01-16

申请人： Po-Tsang Huang ,  Wen-Yen Liu ,  Wei Hwang

发明人： Po-Tsang Huang ,  Wen-Yen Liu ,  Wei Hwang

IPC分类号： G11C7/00

CPC分类号： G11C15/04

摘要： A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.

摘要翻译： 提供一种用于三元内容可寻址存储器的漏电流截止装置。 三元内容可寻址存储器的存储单元可以处于活动模式，数据保持模式和截止模式。 本发明将多模式数据保持电源门控装置应用于三元内容可寻址存储器的存储单元，以减少在数据保持模式和截止模式下通过存储单元的泄漏电流，并且支持全速操作 处于活动模式。