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109 条记录 (耗时 0.025 秒)

    LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE
    2.
    发明申请
    LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE 有权
    具有降低钳位电压的低电容瞬态电压抑制器（TVS）

    公开(公告)号：US20130001694A1

    公开(公告)日：2013-01-03

    申请号：US13170965

    申请日：2011-06-28

    申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

    发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

    IPC分类号： H01L23/60 ,  H01L21/336

    CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

    摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

    摘要翻译： 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。

    Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path
    3.
    发明申请
    Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path 有权
    埋地场环形场效应晶体管（BUF-FET）与注入孔供电路径的电池集成

    公开(公告)号：US20130049102A1

    公开(公告)日：2013-02-28

    申请号：US13199381

    申请日：2011-08-25

    申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

    发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

    摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

    摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

    High voltage field balance metal oxide field effect transistor (FBM)
    4.
    发明授权
    High voltage field balance metal oxide field effect transistor (FBM) 有权
    高电压场平衡金属氧化物场效应晶体管（FBM）

    公开(公告)号：US08785279B2

    公开(公告)日：2014-07-22

    申请号：US13561523

    申请日：2012-07-30

    申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

    发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 一种形成在半导体衬底中的半导体功率器件，包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽，所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Dual-gate trench IGBT with buried floating P-type shield
    7.
    发明授权
    Dual-gate trench IGBT with buried floating P-type shield 有权
    双栅极沟槽IGBT，埋入浮动P型屏蔽

    公开(公告)号：US09048282B2

    公开(公告)日：2015-06-02

    申请号：US13831066

    申请日：2013-03-14

    申请人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    IPC分类号： H01L29/66 ,  H01L29/739

    CPC分类号： H01L29/7395 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66333

    摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

    摘要翻译： 一种制造绝缘栅双极晶体管（IGBT）器件的方法，包括：1）制备具有第一导电类型的外延层的半导体衬底，该半导体衬底支撑在第二导电类型的半导体衬底上; 2）施加栅极沟槽掩模以打开第一沟槽和第二沟槽，随后形成栅极绝缘层以衬垫沟槽并用多晶硅层填充沟槽以形成第一沟槽栅极和第二沟槽栅极; 3）注入第一导电类型的掺杂剂以在外延层中形成上重掺杂区; 以及4）在所述第一沟槽栅极的顶部上形成平面栅极，并且将注入掩模施加到植入物体掺杂剂和源掺杂剂以在所述半导体衬底的顶表面附近形成体区域和源极区域。

    High voltage fast recovery trench diode
    8.
    发明授权
    High voltage fast recovery trench diode 有权

    公开(公告)号：US08710585B1

    公开(公告)日：2014-04-29

    申请号：US13776497

    申请日：2013-02-25

    申请人： Jun Hu ,  Karthik Padmanabhan ,  Madhur Bobde ,  Hamza Yilmaz

    发明人： Jun Hu ,  Karthik Padmanabhan ,  Madhur Bobde ,  Hamza Yilmaz

    IPC分类号： H01L29/66

    CPC分类号： H01L29/0615 ,  H01L21/02104 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/861

    摘要： Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD
    9.
    发明申请
    DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD 有权
    双栅双极型IGBT，带有浮动P型屏蔽

    公开(公告)号：US20140264433A1

    公开(公告)日：2014-09-18

    申请号：US13831066

    申请日：2013-03-14

    申请人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    IPC分类号： H01L29/739 ,  H01L29/66

    CPC分类号： H01L29/7395 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66333

    摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

    摘要翻译： 一种制造绝缘栅双极晶体管（IGBT）器件的方法，包括：1）制备具有第一导电类型的外延层的半导体衬底，该半导体衬底支撑在第二导电类型的半导体衬底上; 2）施加栅极沟槽掩模以打开第一沟槽和第二沟槽，随后形成栅极绝缘层以衬垫沟槽并用多晶硅层填充沟槽以形成第一沟槽栅极和第二沟槽栅极; 3）注入第一导电类型的掺杂剂以在外延层中形成上重掺杂区; 以及4）在所述第一沟槽栅极的顶部上形成平面栅极，并且将注入掩模施加到植入物体掺杂剂和源掺杂剂以在所述半导体衬底的顶表面附近形成体区域和源极区域。

    Dual-gate trench IGBT with buried floating P-type shield
    10.
    发明授权
    Dual-gate trench IGBT with buried floating P-type shield 有权

    公开(公告)号：US10199455B2

    公开(公告)日：2019-02-05

    申请号：US15600782

    申请日：2017-05-21

    申请人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

    IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265

    摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.