公开(公告)号：US08698196B2

公开(公告)日：2014-04-15

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L29/66 ,  H01L29/06

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

公开(公告)号：US20130001694A1

公开(公告)日：2013-01-03

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L23/60 ,  H01L21/336

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

摘要翻译： 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。

公开(公告)号：US20130049102A1

公开(公告)日：2013-02-28

申请号：US13199381

申请日：2011-08-25

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

公开(公告)号：US08785279B2

公开(公告)日：2014-07-22

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种形成在半导体衬底中的半导体功率器件，包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽，所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08575685B2

公开(公告)日：2013-11-05

申请号：US13199381

申请日：2011-08-25

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

公开(公告)号：US20140027841A1

公开(公告)日：2014-01-30

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20160005809A1

公开(公告)日：2016-01-07

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

公开(公告)号：US20130001695A1

公开(公告)日：2013-01-03

申请号：US13171037

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0814 ,  H01L27/082

摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

摘要翻译： 外延层支撑在基板的顶部。 第一和第二体区域形成在外延层中以预定的横向距离分开。 在外延层内形成触发源区和源极区。 第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。 第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。 第三源区域与第四触发区域横向相邻。 第四触发区域在第二和第三源区之间。 第四触发区域内的植入区域与第三源区域横向相邻。

公开(公告)号：US20170213887A1

公开(公告)日：2017-07-27

申请号：US15479281

申请日：2017-04-05

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L29/49 ,  H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

公开(公告)号：US09685523B2

公开(公告)日：2017-06-20

申请号：US14573187

申请日：2014-12-17

申请人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

发明人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

IPC分类号： H01L29/868 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739

CPC分类号： H01L29/868 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7839 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/8725

摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.