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公开(公告)号:US12160993B2
公开(公告)日:2024-12-03
申请号:US18460462
申请日:2023-09-01
Applicant: Lodestar Licensing Group, LLC
Inventor: Yifen Liu , Tecla Ghilardi , George Matamis , Justin D. Shepherdson , Nancy M. Lomeli , Chet E. Carter , Erik R. Byers
IPC: H10B43/27 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
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2.
公开(公告)号:US20240164092A1
公开(公告)日:2024-05-16
申请号:US18389988
申请日:2023-12-20
Applicant: Lodestar Licensing Group, LLC
Inventor: Collin Howder , Chet E. Carter
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20250063733A1
公开(公告)日:2025-02-20
申请号:US18933895
申请日:2024-10-31
Applicant: Lodestar Licensing Group LLC
Inventor: Yifen Liu , Tecla Ghilardi , George Matamis , Justin D. Shepherdson , Nancy M. Lomeli , Chet E. Carter , Erik R. Byers
IPC: H10B43/27 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
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4.
公开(公告)号:US12185545B2
公开(公告)日:2024-12-31
申请号:US18212899
申请日:2023-06-22
Applicant: Lodestar Licensing Group LLC
Inventor: Collin Howder , Chet E. Carter
IPC: H10B43/27 , H01L21/822 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20230413563A1
公开(公告)日:2023-12-21
申请号:US18460462
申请日:2023-09-01
Applicant: Lodestar Licensing Group, LLC
Inventor: Yifen Liu , Tecla Ghilardi , George Matamis , Justin D. Shepherdson , Nancy M. Lomeli , Chet E. Carter , Erik R. Byers
IPC: H10B43/27 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522 , H10B41/27 , H10B41/35 , H10B43/35
CPC classification number: H10B43/27 , H01L21/76877 , H01L23/5283 , H01L23/53257 , H01L23/53271 , H01L21/76816 , H01L23/5226 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号:US11871566B2
公开(公告)日:2024-01-09
申请号:US17590052
申请日:2022-02-01
Applicant: Lodestar Licensing Group, LLC
Inventor: Collin Howder , Chet E. Carter
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.
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