公开(公告)号：US20250063733A1

公开(公告)日：2025-02-20

申请号：US18933895

申请日：2024-10-31

Applicant: Lodestar Licensing Group LLC

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230363168A1

公开(公告)日：2023-11-09

申请号：US18353794

申请日：2023-07-17

Applicant: Lodestar Licensing Group, LLC

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

公开(公告)号：US12010850B2

公开(公告)日：2024-06-11

申请号：US18218762

申请日：2023-07-06

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Justin B. Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240008275A1

公开(公告)日：2024-01-04

申请号：US18218762

申请日：2023-07-06

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Justin Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B43/35 ,  H10B41/35 ,  H10B43/10 ,  H10B41/27

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12302571B2

公开(公告)日：2025-05-13

申请号：US18353794

申请日：2023-07-17

Applicant: Lodestar Licensing Group, LLC

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

公开(公告)号：US20240397717A1

公开(公告)日：2024-11-28

申请号：US18735864

申请日：2024-06-06

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Justin B. Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230413563A1

公开(公告)日：2023-12-21

申请号：US18460462

申请日：2023-09-01

Applicant: Lodestar Licensing Group, LLC

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53271 ,  H01L21/76816 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US12160993B2

公开(公告)日：2024-12-03

申请号：US18460462

申请日：2023-09-01

Applicant: Lodestar Licensing Group, LLC

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20240349498A1

公开(公告)日：2024-10-17

申请号：US18752438

申请日：2024-06-24

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27 ,  H10B43/50

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11894269B2

公开(公告)日：2024-02-06

申请号：US17577031

申请日：2022-01-17

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2221/1063

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.