公开(公告)号：US12185545B2

公开(公告)日：2024-12-31

申请号：US18212899

申请日：2023-06-22

Applicant: Lodestar Licensing Group LLC

Inventor： Collin Howder ,  Chet E. Carter

IPC: H10B43/27 ,  H01L21/822 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240153877A1

公开(公告)日：2024-05-09

申请号：US18402618

申请日：2024-01-02

Applicant: Lodestar Licensing Group LLC

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11871566B2

公开(公告)日：2024-01-09

申请号：US17590052

申请日：2022-02-01

Applicant: Lodestar Licensing Group, LLC

Inventor： Collin Howder ,  Chet E. Carter

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12167600B2

公开(公告)日：2024-12-10

申请号：US18140516

申请日：2023-04-27

Applicant: Lodestar Licensing Group LLC

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US12063782B2

公开(公告)日：2024-08-13

申请号：US17941900

申请日：2022-09-09

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US20250107090A1

公开(公告)日：2025-03-27

申请号：US18967343

申请日：2024-12-03

Applicant: Lodestar Licensing Group LLC

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US20240164092A1

公开(公告)日：2024-05-16

申请号：US18389988

申请日：2023-12-20

Applicant: Lodestar Licensing Group, LLC

Inventor： Collin Howder ,  Chet E. Carter

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.