公开(公告)号：US12004351B2

公开(公告)日：2024-06-04

申请号：US17869732

申请日：2022-07-20

申请人： Lodestar Licensing Group LLC

发明人： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC分类号： H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC分类号： H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240324223A1

公开(公告)日：2024-09-26

申请号：US18731940

申请日：2024-06-03

申请人： Lodestar Licensing Group LLC

发明人： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC分类号： H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC分类号： H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12089403B2

公开(公告)日：2024-09-10

申请号：US17590266

申请日：2022-02-01

申请人： Lodestar Licensing Group LLC

发明人： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC分类号： H10B41/27 ,  H01L21/311 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B41/27 ,  H01L21/31144 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20230413563A1

公开(公告)日：2023-12-21

申请号：US18460462

申请日：2023-09-01

申请人： Lodestar Licensing Group, LLC

发明人： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC分类号： H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53271 ,  H01L21/76816 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

摘要： A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.