公开(公告)号：US20080002446A1

公开(公告)日：2008-01-03

申请号：US11758529

申请日：2007-06-05

申请人： Lorenzo Selgi ,  Leonardo Fragapane ,  Luigi Arcuri

发明人： Lorenzo Selgi ,  Leonardo Fragapane ,  Luigi Arcuri

IPC分类号： H02M1/00

CPC分类号： H02M1/36 ,  H02M3/33507 ,  Y10S323/901

摘要： An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.

摘要翻译： 一种用于控制负载的电子设备包括：具有要连接到所述负载的输出端子的高压集成开关; 用于驱动开关的集成和低压驱动电路，以及包括高压电阻器的启动集成电路，并且使得能够在打开电源装置的步骤期间使能，以激活 驱动电路。 开关和启动电路集成在第一半导体芯片中，并且驱动电路集成在不同的第二半导体芯片中。

公开(公告)号：US07782637B2

公开(公告)日：2010-08-24

申请号：US11758529

申请日：2007-06-05

申请人： Lorenzo Maurizio Selgi ,  Leonardo Fragapane ,  Luigi Arcuri

发明人： Lorenzo Maurizio Selgi ,  Leonardo Fragapane ,  Luigi Arcuri

IPC分类号： H02M7/10 ,  H02M1/00

CPC分类号： H02M1/36 ,  H02M3/33507 ,  Y10S323/901

摘要： An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.

摘要翻译： 一种用于控制负载的电子设备包括：具有要连接到所述负载的输出端子的高压集成开关; 用于驱动开关的集成和低压驱动电路，以及包括高压电阻器的启动集成电路，并且使得能够在打开电源装置的步骤期间使能，以激活 驱动电路。 开关和启动电路集成在第一半导体芯片中，并且驱动电路集成在不同的第二半导体芯片中。

公开(公告)号：US06222248B1

公开(公告)日：2001-04-24

申请号：US09490589

申请日：2000-01-25

申请人： Leonardo Fragapane

发明人： Leonardo Fragapane

IPC分类号： H01L27082

CPC分类号： H01L29/1095 ,  H01L27/0611 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00

摘要： A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.

摘要翻译： 一种器件，包括形成在由包含第一P型区域和端接结构的N型外延层的P型衬底组成的硅芯片上的IGBT a，并且具有包围第一区域的第一P型端接区域， 与第一端接区域接触的第一电极，以及靠近芯片边缘的框架形式的第二电极，并且连接到与芯片底部接触的第三电极。 与第一电极一体制成的第四电极与第一区域接触。 所述端接结构还包括与外延层接触的第五电极，所述第五电极沿着平行于所述第一端接区域的边缘并连接到所述第二电极的路径以及围绕所述第五电极和第六电极的第二P型端接区域，以及 其与第二端接区域接触，连接到第一电极。

公开(公告)号：US07091559B2

公开(公告)日：2006-08-15

申请号：US10817742

申请日：2004-04-01

申请人： Leonardo Fragapane ,  Antonino Alessandria

发明人： Leonardo Fragapane ,  Antonino Alessandria

IPC分类号： H01L29/72

CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L27/0788 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7395

摘要： A junction device including at least a first type semiconductor region and a second type semiconductor region a, which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (; the device is moreover provided with a resistive region, which has the first type of conductivity and extends from the first type semiconductor region and is contiguous to the second type semiconductor region so as to form a resistive path between the first and the second biasing regions.

摘要翻译： 包括至少第一类型半导体区域和第二类型半导体区域a的连接装置，它们彼此相邻并且具有彼此相对的第一和第二类型的导电性，并且第一 以及第二偏置区域（该器件还设置有电阻区域，该电阻区域具有第一类型的导电性，并且从第一类型半导体区域延伸并且与第二类型半导体区域邻接，以形成第二类型半导体区域之间的电阻路径） 第一和第二偏压区域。

公开(公告)号：US06271061B1

公开(公告)日：2001-08-07

申请号：US09354880

申请日：1999-07-16

申请人： Ferruccio Frisina ,  Leonardo Fragapane

发明人： Ferruccio Frisina ,  Leonardo Fragapane

IPC分类号： H01L21332

CPC分类号： H01L29/66333 ,  H01L29/7395

摘要： A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

摘要翻译： 一种半导体功率器件，包括绝缘栅双极晶体管，其类型包括具有第一导电类型的半导体衬底和具有与第一导电相反的第二导电类型的上覆外延层，并且其与衬底的结到其形成 双极晶体管的基极/发射极结具有由具有第二类型的导电性但具有比外延层更高的掺杂剂浓度的半导体材料层形成的结。 此外，器件具有第二类型的具有导电性的外延层，其具有不同掺杂剂浓度的至少两个区域，即，第一下部区域是结的一部分并且具有较高的掺杂剂浓度，以及具有较低掺杂剂浓度的第二上部区域 浓度。

公开(公告)号：US08637369B2

公开(公告)日：2014-01-28

申请号：US13409411

申请日：2012-03-01

申请人： Angelo Magri ,  Antonino Sebastiano Alessandria ,  Stefania Fortuna ,  Leonardo Fragapane

发明人： Angelo Magri ,  Antonino Sebastiano Alessandria ,  Stefania Fortuna ,  Leonardo Fragapane

IPC分类号： H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： An embodiment of a method for manufacturing a power device with conductive gate structures inside etched trenches. Such trenches include sidewalls and a bottom, wherein covering the sidewalls and the bottom of the trench is a first insulating coating layer. In the formation of the conductive gate structure, openings within the first material in the trench are made such that a conductive central region of a second conductive material having a different resistivity than the first conductive material are able to be electrically coupled together through a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

摘要翻译： 用于制造在蚀刻沟槽内部具有导电栅极结构的功率器件的方法的实施例。 这种沟槽包括侧壁和底部，其中覆盖沟槽的侧壁和底部是第一绝缘涂层。 在导电栅极结构的形成中，沟槽中的第一材料内的开口被制成使得具有与第一导电材料不同的电阻率的第二导电材料的导电中心区域能够通过多个 所述第二导电涂层和所述导电中心区之间的导电桥。

公开(公告)号：US06169300A

公开(公告)日：2001-01-02

申请号：US09034391

申请日：1998-03-04

申请人： Leonardo Fragapane

发明人： Leonardo Fragapane

IPC分类号： H01L2974

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/7395

摘要： An Insulated Gate Bipolar Transistor includes a semiconductor substrate of a first conductivity type forming a first electrode of the device, a semiconductor layer of a second conductivity type superimposed over said substrate, a plurality of body regions of the first conductivity type formed in the semiconductor layer, a first doped region of the second conductivity type formed inside each body region, an insulated gate layer superimposed over portions of the semiconductor layer between the body regions and forming a control electrode of the device, a conductive layer insulatively disposed over the insulated gate layer and contacting each body region and each doped region formed therein, the conductive layer forming a second electrode of the device. In the portions of the semiconductor layer between the body regions second doped regions of the first conductivity type are formed, and openings are provided in the insulated gate layer at the second doped regions to allow the conductive layer to contact the second doped regions.

摘要翻译： 绝缘栅双极晶体管包括形成器件的第一电极的第一导电类型的半导体衬底，叠加在所述衬底上的第二导电类型的半导体层，形成在半导体层中的多个第一导电类型的体区 形成在每个体区内的第二导电类型的第一掺杂区，在所述体区之间叠加在所述半导体层的部分上并形成所述器件的控制电极的绝缘栅层，绝缘地设置在所述绝缘栅层上的导电层 并且接触每个体区和形成在其中的每个掺杂区，所述导电层形成该器件的第二电极。 在主体区域中形成第一导电类型的第二掺杂区域之间的半导体层的部分，并且在第二掺杂区域处的绝缘栅极层中设置开口以允许导电层与第二掺杂区域接触。

公开(公告)号：USRE40222E1

公开(公告)日：2008-04-08

申请号：US10423493

申请日：2003-04-24

申请人： Leonardo Fragapane

发明人： Leonardo Fragapane

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/1095 ,  H01L27/0611 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00

摘要： A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.

摘要翻译： 一种器件，包括形成在由包含第一P型区域和端接结构的N型外延层的P型衬底组成的硅芯片上的IGBT，并且具有包围第一区域的第一P型端接区域的器件， 与第一端接区域接触的第一电极和第二电极，其形状为靠近芯片边缘的框架形状，并连接到与芯片底部接触的第三电极。 与第一电极一体制成的第四电极与第一区域接触。 所述端接结构还包括与外延层接触的第五电极，所述第五电极沿着平行于所述第一端接区域的边缘并连接到所述第二电极的路径以及围绕所述第五电极和第六电极的第二P型端接区域，以及 其与第二端接区域接触，连接到第一电极。

公开(公告)号：US07205607B2

公开(公告)日：2007-04-17

申请号：US10993917

申请日：2004-11-19

申请人： Antonino Sebastiano Alessandria ,  Leonardo Fragapane ,  Angelo Magri

发明人： Antonino Sebastiano Alessandria ,  Leonardo Fragapane ,  Angelo Magri

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.

摘要翻译： 半导体功率器件包括绝缘栅极和沟槽栅极结构。 沟槽栅结构形成在被外延层覆盖的半导体衬底上。 在半导体中形成沟槽以形成器件栅极区域。 介电涂层设置在沟槽的内壁和底壁上。 栅极区域仅在沟槽的内壁上的涂层上包括导电间隔层。

公开(公告)号：US5963407A

公开(公告)日：1999-10-05

申请号：US020420

申请日：1998-02-09

申请人： Leonardo Fragapane ,  Romeo Letor

发明人： Leonardo Fragapane ,  Romeo Letor

IPC分类号： H03K17/082 ,  H02H3/00

CPC分类号： H03K17/0822 ,  H03K17/0828

摘要： A fast operating, electronic overvoltage protection device intended for a power transistor having at least one control terminal of the MOS type is disclosed. The device comprises a Zener diode associated with the power transistor and integrated together therewith in a semiconductor substrate, and a second transistor connected to the power transistor into a Darlington configuration and also connected to the Zener diode. The protection from overvoltages provided by the device is very fast in operation, and can be implemented in integrated form at reduced cost and without introducing parasitic elements.

摘要翻译： 公开了一种用于具有MOS类型的至少一个控制端的功率晶体管的快速操作的电子过电压保护装置。 该器件包括与功率晶体管相关并且与半导体衬底集成在一起的齐纳二极管，以及连接到功率晶体管为达林顿配置并且还连接到齐纳二极管的第二晶体管。 由器件提供的过电压保护在操作上非常快速，并且可以以降低成本并且不引入寄生元件的集成形式来实现。