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公开(公告)号：US6016517A
公开(公告)日：2000-01-18
申请号：US827743
申请日：1997-04-10
IPC分类号： G06F1/22 , H03K19/173 , G06F13/00
CPC分类号： G06F1/22 , H03K19/1732
摘要： A connector on a printed circuit board of a computer system is reused to reduce a number of connectors utilized on a motherboard of a computer system. By recognizing that some signals are common between a programming application performed during a manufacturing process and a second application performed while the computer system is a normal customer operation, the connector may be used to provide data values during both the manufacturing process and normal customer operation. Stated another way, data signals used to drive programmed data during the manufacturing process may be re-used to provide serial data to an input/output device during normal customer operation.
摘要翻译： 重新使用计算机系统的印刷电路板上的连接器来减少在计算机系统的主板上使用的多个连接器。 通过认识到在制造过程中执行的编程应用和在计算机系统是正常客户操作期间执行的第二应用之间的一些信号是共同的，连接器可以用于在制造过程和正常客户操作期间提供数据值。 换句话说，用于在制造过程中驱动编程数据的数据信号可能被重新用于在正常的客户操作期间向输入/输出设备提供串行数据。
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公开(公告)号：US6115773A
公开(公告)日：2000-09-05
申请号：US159958
申请日：1998-09-24
CPC分类号： G06F13/4086
摘要： A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.
摘要翻译： 总线终端阻抗验证电路。 验证电路包括由感测输入节点和感测输出节点组成的检测电路。 感测电路的感测节点连接到总线的信号导体，以检测总线的终端阻抗。 当感测电路输入节点被激活时，感测输出节点的电压指示总线的终端阻抗。 比较器电路包括比较器输入节点和比较器输出节点。 比较器输入节点连接到感测电路输出节点。 比较器电路被配置为使得比较器输出节点指示比较器输入节点的电压是否在规定的电压范围内。 由感测电路检测到的信号导体的电压将是连接到总线的终端电路的阻抗的函数。 连接到总线的终端电路的过剩或不足将导致检测到的控制信号电压不在规定的限度内。
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公开(公告)号：US5953243A
公开(公告)日：1999-09-14
申请号：US164131
申请日：1998-09-30
CPC分类号： G11C5/06 , G06F11/006 , G06F13/4239 , G11C5/04
摘要： A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.
摘要翻译： 计算机系统包括具有能够接收DRAM和SDRAM存储器模块设备的DIMM插槽的存储器子系统。 存储器件检测方法检测存储器模块插槽中存在的已安装的存储器模块，并且处理所安装的存储器模块的预定引脚上的信号电平以识别所安装的存储器模块的具体类型。 相关联的存储器控制器的模式根据检测到的模块的类型来设置，并且读取存储器模块的特性。
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公开(公告)号：US5961660A
公开(公告)日：1999-10-05
申请号：US808771
申请日：1997-03-03
CPC分类号： G06F11/1048 , H03M13/35
摘要： A method and apparatus for providing a memory system having error checking and correction (ECC) capability, and parity error detection capability on the same memory card, and user selection of either capability using the same type of memory modules. A memory controller having programmable configuration registers is provide for user selection of either ECC or parity capability. Eight-byte Dual in-line Memory Modules are used to provide 64-bit data which allows the memory controller to use eight extra bits for both ECC and parity capability.
摘要翻译： 一种用于提供具有错误检查和校正（ECC）能力的存储器系统以及同一存储卡上的奇偶校验错误检测能力的方法和装置，以及使用相同类型的存储器模块的用户选择任一能力。 具有可编程配置寄存器的存储器控制器被提供用于ECC或奇偶校验能力的选择。 八字节双列直插式存储器模块用于提供64位数据，允许存储器控制器使用八个额外的位用于ECC和奇偶校验能力。
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5.发明授权Method and apparatus for driving a battery-backed up clock while a system is powered-down 失效在系统关机时驱动电池备用时钟的方法和装置
公开(公告)号：US6069850A
公开(公告)日：2000-05-30
申请号：US40430
申请日：1998-03-18
摘要： A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.
摘要翻译： 一种用于在计算机系统断电时驱动电池备份的时钟的方法和装置。 本发明使用辅助电源VAUX为微处理器总线振荡器供电。 微处理器总线振荡器通常是高频率，高精度的振荡器。 当计算机系统掉电时，微处理器总线振荡器继续运行，但连接到墙上插座。 因此，它可以用于合成准确的时基来驱动电池备份的时钟输入。 可以使用微控制器，PAL或其它这样的电路将来自微处理器总线振荡器的高频信号转换成适合于电池备份时钟的频率。 因此，使用单个振荡器来保持正常操作的时间。 只有当系统移动或主电源故障时，才能使用电池备份的晶体振荡器来保持时间。 由于系统被关闭并重新启动，因此最小化定时错误的发生。
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6.发明授权Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution 有权通过对单线程程序执行前瞻性操作来在执行之前识别多条指令线程来并行化单线程程序公开(公告)号：US08495636B2
公开(公告)日：2013-07-23
申请号：US11959906
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译： 一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令， 并分配空闲核心以执行推测性指令。
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公开(公告)号：US08379847B2
公开(公告)日：2013-02-19
申请号：US12828080
申请日：2010-06-30
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译： 设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据 由密钥定义的加密顺序。 加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。
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公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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9.发明授权System and method to optimize multi-core microprocessor performance using voltage offsets 失效使用电压补偿优化多核微处理器性能的系统和方法公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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10.发明授权Method and apparatus for controlling heat generation in a multi-core processor 有权用于控制多核处理器中的发热的方法和装置公开(公告)号：US07617403B2
公开(公告)日：2009-11-10
申请号：US11459988
申请日：2006-07-26
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以减少多核处理器中的发热。 在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。 所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。
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