公开(公告)号：US20060067440A1

公开(公告)日：2006-03-30

申请号：US10711713

申请日：2004-09-30

申请人： Louis Hsu ,  Brian Ji ,  James Mason ,  Karl Selander ,  Michael Sorna ,  Steven Zier

发明人： Louis Hsu ,  Brian Ji ,  James Mason ,  Karl Selander ,  Michael Sorna ,  Steven Zier

IPC分类号： H03K5/01 ,  H04B1/10 ,  H04L25/08

CPC分类号： H04L25/085 ,  H03F1/3241 ,  H04L25/0278 ,  H04L25/0292 ,  H04L25/03343 ,  H04L25/061 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03808

摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.

摘要翻译： 提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。 接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

公开(公告)号：US20050281343A1

公开(公告)日：2005-12-22

申请号：US10710064

申请日：2004-06-16

申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Jeremy Stephens ,  Huihao Xu

发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Jeremy Stephens ,  Huihao Xu

IPC分类号： H04L25/00 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03343

摘要： A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

摘要翻译： 数据通信系统包括发射机单元和接收机单元。 发送单元具有根据均衡信息可调的传输特性。 发送单元可操作以发送预定信号，并且接收器单元可操作以接收预定信号。 接收机单元进一步可操作以通过检查接收到的信号的眼图来产生均衡信息，并将均衡信息发送到发射机单元。

公开(公告)号：US20060159200A1

公开(公告)日：2006-07-20

申请号：US10905705

申请日：2005-01-18

申请人： Louis Hsu ,  Matt Cordrey-Gale ,  James Mason ,  Phillip Murfet ,  Karl Selander ,  Michael Sorna ,  Huihao Xu

发明人： Louis Hsu ,  Matt Cordrey-Gale ,  James Mason ,  Phillip Murfet ,  Karl Selander ,  Michael Sorna ,  Huihao Xu

IPC分类号： H04L27/22

CPC分类号： H04L25/0274 ,  H04L25/0296

摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

摘要翻译： 提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。 前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。 前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输 偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收 偏移补偿电路使能的模式。

公开(公告)号：US20060158229A1

公开(公告)日：2006-07-20

申请号：US10905704

申请日：2005-01-18

申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna

发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna

IPC分类号： H03K5/19

CPC分类号： H03K5/19 ,  G01R19/165

摘要： An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

摘要翻译： 改进的信号检测器系统可实现在高速SerDes接收机核心中，能够以更严格的公差检测来自噪声信号的有效信号。 信号检测器系统通过实施修改来改进现有技术的设计，包括：（1）使用两个峰值放大器用于（差分）输入信号和参考跟踪和消除增益变化; 和（2）减少当前镜像阶段以减少当前的映射误差。

公开(公告)号：US20060274681A1

公开(公告)日：2006-12-07

申请号：US10908959

申请日：2005-06-02

申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

IPC分类号： H04B1/58

CPC分类号： G06F13/4072

摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.

摘要翻译： 提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。 信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。 信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。 通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。 优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

公开(公告)号：US20050179486A1

公开(公告)日：2005-08-18

申请号：US11103314

申请日：2005-04-11

申请人： Hibourahima Camara ,  Louis Hsu ,  Karl Selander ,  Michael Sorna

发明人： Hibourahima Camara ,  Louis Hsu ,  Karl Selander ,  Michael Sorna

IPC分类号： G05F1/565 ,  H03K4/06

CPC分类号： G05F1/565

摘要： Systems are provided for generating and distributing a plurality of reference currents on an integrated circuit. More particularly, an integrated circuit is provided which includes a reference current generating system. The reference current generating system includes a first reference current generator disposed at a first location of the integrated circuit which is operable to generate a plurality of first reference currents. A plurality of second reference current generators are disposed at a plurality of second locations of the integrated circuit. Each of the second reference current generators are operable to generate a second reference current from one of the plurality of first reference currents. In a particular example, the first location at which the first reference current generator is disposed is a central location and the second locations are disposed remote from the first location.

摘要翻译： 提供了用于在集成电路上生成和分配多个参考电流的系统。 更具体地，提供了包括参考电流产生系统的集成电路。 参考电流产生系统包括设置在集成电路的第一位置处的第一参考电流发生器，其可操作以产生多个第一参考电流。 多个第二参考电流发生器设置在集成电路的多个第二位置处。 每个第二参考电流发生器可操作以从多个第一参考电流之一产生第二参考电流。 在特定示例中，设置第一参考电流发生器的第一位置是中心位置，并且第二位置远离第一位置设置。

公开(公告)号：US20060045224A1

公开(公告)日：2006-03-02

申请号：US10915790

申请日：2004-08-11

申请人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

发明人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L2207/50

摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。

公开(公告)号：US20060109940A1

公开(公告)日：2006-05-25

申请号：US10994742

申请日：2004-11-22

申请人： Troy Beukema ,  Benjamin Parker ,  Karl Selander ,  Michael Sorna

发明人： Troy Beukema ,  Benjamin Parker ,  Karl Selander ,  Michael Sorna

IPC分类号： H04L7/00 ,  H04B1/10

CPC分类号： H04L25/03057 ,  H04L7/0058 ,  H04L7/0334 ,  H04L2025/0349

摘要： A phase adjustment apparatus and method adjusts phase or timing bias of a sample clock in a data receiver system by determining a time adjustment value as a function of equalizer feedback. The time adjustment value is then applied to a device capable of adjusting a timing bias of a sample clock.

摘要翻译： 相位调整装置和方法通过确定作为均衡器反馈的函数的时间调整值来调整数据接收机系统中采样时钟的相位或定时偏置。 然后将时间调整值应用于能够调整采样时钟的定时偏置的装置。

公开(公告)号：US20070164768A1

公开(公告)日：2007-07-19

申请号：US11306985

申请日：2006-01-18

申请人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

发明人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.

摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间，将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。

公开(公告)号：US20080049819A1

公开(公告)日：2008-02-28

申请号：US11846581

申请日：2007-08-29

申请人： Jon Garlett ,  Victor Moy ,  Michael Sorna

发明人： Jon Garlett ,  Victor Moy ,  Michael Sorna

IPC分类号： H04B3/46

CPC分类号： H04B17/20 ,  H04B17/101 ,  H04B17/19

摘要： A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

摘要翻译： 数据通信系统包括确保组件响应于高速数据通信信号的有效数据窗口或“眼睛”的时间长度变化的电路。 系统的自检部分周期性地将相位抖动的影响注入到数据通信信号中，以确保系统正常运行。