公开(公告)号：US07216284B2

公开(公告)日：2007-05-08

申请号：US10145018

申请日：2002-05-15

申请人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G11C29/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.

摘要翻译： 内容可寻址存储器（CAM）。 CAM阵列的数据部分包括字数据存储。 每个字线包括数据部分中的CAM单元（动态或静态）和公共字匹配线。 CAM阵列的纠错（例如，奇偶校验）部分包含每个字线的纠错单元。 每个字线处的误差校正单元连接到纠错匹配线。 纠错匹配线上的匹配可以对相应的数据匹配线进行预充电。 在数据比较中仅包括在纠错匹配行上具有对应匹配的字线上的数据。 预充电功率只需要一个分数（与所使用的误差校正的位长度成反比成正比）的整数组。

公开(公告)号：US07355872B2

公开(公告)日：2008-04-08

申请号：US10673801

申请日：2003-09-29

申请人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.

摘要翻译： 内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线 ，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

公开(公告)号：US06823293B2

公开(公告)日：2004-11-23

申请号：US10334312

申请日：2002-12-31

申请人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G06F1500

CPC分类号： G01R31/3004 ,  G01R31/31721

摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.

摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。

公开(公告)号：US08198174B2

公开(公告)日：2012-06-12

申请号：US12536176

申请日：2009-08-05

申请人： Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

发明人： Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L21/44

CPC分类号： H01L23/467 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.

摘要翻译： 提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合 在其接合界面处的垂直堆叠的晶片的晶片。 此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过 一个或多个开口以从芯片堆叠结构移除热量。

公开(公告)号：US06252806B1

公开(公告)日：2001-06-26

申请号：US09579749

申请日：2000-05-26

申请人： Wayne F. Ellis ,  Louis L. Hsu ,  Brian L. Ji ,  Yujon Li ,  Oliver Weinfurtner

发明人： Wayne F. Ellis ,  Louis L. Hsu ,  Brian L. Ji ,  Yujon Li ,  Oliver Weinfurtner

IPC分类号： G11C1604

CPC分类号： G11C8/08 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4078 ,  G11C2207/104

摘要： Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

摘要翻译： 通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。 电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。 这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。 性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

公开(公告)号：US07005319B1

公开(公告)日：2006-02-28

申请号：US10993941

申请日：2004-11-19

申请人： Howard Hao Chen ,  Louis L. Hsu ,  Brian L. Ji

发明人： Howard Hao Chen ,  Louis L. Hsu ,  Brian L. Ji

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/16 ,  H01L2221/6835 ,  H01L2224/24227 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  Y10S438/977

摘要： In accordance with the present invention, a method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of the plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved. The method comprises forming at least a first chip on a first dummy carrier and at least a second chip different from the first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing. The method further includes using a chip thickness control mechanism in conjunction with said partial wafer bonding and partial wafer dicing in forming the at least a first chip and at least second chip different from the first chip, such that the at least first chip and the at least second different chip formed from each carrier each have a final total chip thickness (FTC) which is substantially equal to one another, and an FTC which is substantially equal to a total pocket depth (Tdp) of each of the uniform pockets of said wafer chip carrier, minus the final thickness of an attaching material (FTG) used within said each respective pocket.

摘要翻译： 根据本发明，一种用于制造具有受控总芯片厚度的至少两个不同芯片的方法，使得当这些芯片被放置在位于晶片芯片载体中的多个凹穴的相应凹穴中时，其中多个 口袋具有至少基本上彼此相等的总口袋深度（Tdp），实现了所述晶片芯片载体的基本平坦化的顶表面。 该方法包括使用部分晶片接合和部分晶片切割，在第一虚设载体上形成至少第一芯片和至少第二芯片，该第一芯片与第一芯片不同于分开的第二虚设载体。 该方法还包括在形成至少第一芯片和与第一芯片不同的至少第二芯片的同时，使用芯片厚度控制机构与所述部分晶片结合和部分晶片切割相结合，使得至少第一芯片和在 从每个载体形成的最小的第二不同的芯片各自具有彼此基本相等的最终的总芯片厚度（FTC），以及基本上等于所述晶片的每个均匀袋的总袋深度（Tdp）的FTC 芯片载体减去在每个相应的口袋内使用的附着材料（FTG）的最终厚度。

公开(公告)号：US06980824B2

公开(公告)日：2005-12-27

申请号：US10249546

申请日：2003-04-17

申请人： Louis L. Hsu ,  Brian L. Ji ,  Karl D. Selander ,  Michael A. Sorna

发明人： Louis L. Hsu ,  Brian L. Ji ,  Karl D. Selander ,  Michael A. Sorna

IPC分类号： H04B7/005 ,  H04B7/00

CPC分类号： H04W52/20

摘要： A method and system are disclosed herein for determining optimum power level settings for a transmitter and receiver pair of a communication system having a plurality of transmitter and receiver pairs, as determined with respect to bit error rate. In the method disclosed herein, the power levels of a transmitter and a receiver pair coupled to communicate over a duplex communication link are set to initial values. The bit error rate is then determined over the link. Then, the power level of the transmitter, the receiver, or both, is altered, incrementally, and the effect upon the bit error rate is determined. When an improvement appears in the bit error rate at an altered power level, the power level of the transmitter, the receiver or both, are set to the altered power level at which the improvement is found. The steps of incrementally altering power levels, determining the bit error rate, and establishing new power level settings when there is an improvement are repeated until power levels are determined at which the bit error rate is optimized.

摘要翻译： 本文公开了一种用于确定具有多个发射机和接收机对的通信系统的发射机和接收机对的最佳功率电平设置的方法和系统，如针对误码率确定的。 在本文公开的方法中，耦合到通过双工通信链路进行通信的发射机和接收机对的功率电平被设置为初始值。 然后通过链路确定误码率。 然后，发送器，接收器或两者的功率电平被改变，递增地，并且确定对误码率的影响。 当在改变的功率电平上出现比特错误率的改进时，发射机，接收机或两者的功率电平被设置为发现改进的改变的功率电平。 重复改变功率级别，确定误码率和建立新的功率电平设置的步骤，直到确定位误码率被优化的功率电平为止。

公开(公告)号：US06975140B2

公开(公告)日：2005-12-13

申请号：US10707199

申请日：2003-11-26

申请人： Louis L. Hsu ,  Brian L. Ji ,  William F. Washburn

发明人： Louis L. Hsu ,  Brian L. Ji ,  William F. Washburn

IPC分类号： H03H21/00 ,  H04L25/03 ,  H04L27/04 ,  H03H19/0175

CPC分类号： H04L25/03343 ,  H03H21/0012

摘要： A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.

摘要翻译： 提供了一种数据发送器和发送方法，其中自适应有限脉冲响应（FIR）驱动器具有应用具有可更新值的系数的多个抽头。 FIR驱动器在数据位的输入流和数据位的输出流之间具有传递函数，使得从FIR驱动器输出的每个数据位的幅度根据输入的多个数据位的值而被调整 流，以及系数的值。 数据发送器包括可重写的非易失性存储器，可操作以用表示在FIR驱动器的操作期间更新的系数的值的控制信息进行重写。

公开(公告)号：US08766410B2

公开(公告)日：2014-07-01

申请号：US13153806

申请日：2011-06-06

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L23/58

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

公开(公告)号：US08212537B2

公开(公告)日：2012-07-03

申请号：US12508235

申请日：2009-07-23

申请人： Gary D. Carpenter ,  Wonyoung Kim ,  Brian L. Ji

发明人： Gary D. Carpenter ,  Wonyoung Kim ,  Brian L. Ji

IPC分类号： G05F1/10 ,  G05F1/40

CPC分类号： H02M3/158

摘要： A converter circuit and methods for operating the same. The converter circuit includes a supply voltage, a capacitor, an inductor, and four stacked switching elements. Each switching element is adjustable from a low resistance state to a high resistance state by a control signal. The inductor outputs current to a circuit load. The circuit may be operated in a first mode such that the output is adjustable between the supply voltage and half the supply voltage. Alternatively, in a second mode of operation, the output is adjustable from half the supply voltage to a ground voltage.

摘要翻译： A转换器电路及其操作方法。 转换器电路包括电源电压，电容器，电感器和四个堆叠的开关元件。 每个开关元件可通过控制信号从低电阻状态调节到高电阻状态。 电感将电流输出到电路负载。 电路可以在第一模式下操作，使得输出在电源电压和电源电压的一半之间是可调节的。 或者，在第二操作模式中，输出可从电源电压的一半调整到接地电压。