-
1.发明授权System and method for preventing noise cross contamination between embedded DRAM and system chip 失效嵌入式DRAM与系统芯片之间的噪声交叉污染防止系统和方法公开(公告)号：US06349067B1
公开(公告)日：2002-02-19
申请号：US09772461
申请日：2001-01-30
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C7/18 , G11C2207/104 , H01L21/761 , H01L21/823481 , H01L27/10897
摘要： A complete solution to block noise from eDRAM macro to the analog core, and vice verse, in a system-on-chip IC design. Specifically, there is provided a first isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a DC generator circuit fabricated therein; and, a second isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a noise sense amplifier bank and DRAM arrays fabricated therein. A power supply source is provided for supplying power to each DC generator circuit, noise sense amplifier bank and DRAM array; as is a power bus for providing power and a separate power bus for providing a ground to each of the DC generator circuit, and the noise sense amplifier circuit and DRAM array components. In this manner, noise contamination with noise sensitive devices in said IC is reduced and, further noise contamination of the DRAM array as sourced from the IC is reduced.
摘要翻译： 一种完整的解决方案，可以将eDRAM宏的噪声阻挡到模拟核心，而在片上系统集成电路设计中也是如此。 具体地，提供了一种形成在IC中的用于减少由其中制造的直流发电机电路的操作元件产生的噪声分量的第一隔离三重阱结构; 以及形成在IC中的用于降低噪声检测放大器组的操作元件和其中制造的DRAM阵列产生的噪声分量的第二隔离三重阱结构。 提供电源，用于向每个DC发生器电路，噪声检测放大器组和DRAM阵列供电; 用于提供电力的电源总线和用于向每个DC发电机电路以及噪声检测放大器电路和DRAM阵列组件提供接地的单独的电源总线。 以这种方式，减少了所述IC中噪声敏感器件的噪声污染，并且降低了来自IC的DRAM阵列的进一步的噪声污染。
-
公开(公告)号：US07447273B2
公开(公告)日：2008-11-04
申请号：US10708240
申请日：2004-02-18
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。
-
公开(公告)号：US07041525B2
公开(公告)日：2006-05-09
申请号：US10751205
申请日：2004-01-02
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
-
公开(公告)号：US06629291B1
公开(公告)日：2003-09-30
申请号：US09668977
申请日：2000-09-25
申请人： Russell J. Houghton , Joni C. Hsu , Louis L. Hsu , Li-Kong Wang
发明人： Russell J. Houghton , Joni C. Hsu , Louis L. Hsu , Li-Kong Wang
IPC分类号： G06F1750
CPC分类号： G06F1/28 , G06F17/5045 , G11C5/14
摘要： A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.
摘要翻译： 一种用于多系统片上设备的集中供电系统包括：用于向设备供电的外部电源; 集中式DC发电机宏，其具有用于接收所提供的外部电力并由其产生的一个或多个电源电压，用于由多系统芯片上提供的周围系统宏使用的发电机组件，集中式DC发电机宏进一步将生成的电源电压分配到 各自的系统宏。 提供了围绕集中式DC发电机系统的隔离结构，并将集中式DC发电机系统与周围系统宏隔离开来。
-
5.发明授权Semiconductor memory system having a data clock system for reliable high-speed data transfers 失效具有用于可靠的高速数据传输的数据时钟系统的半导体存储器系统公开(公告)号：US06614714B2
公开(公告)日：2003-09-02
申请号：US10055149
申请日：2002-01-22
IPC分类号： G11C818
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
摘要翻译： 提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。 半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。 数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。 在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。 还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。 在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近， 至少一个时钟驱动器位于第二时钟路径的近端附近。
-
公开(公告)号：US06579743B2
公开(公告)日：2003-06-17
申请号：US10041639
申请日：2002-01-07
IPC分类号： H01L2100
CPC分类号： H01L23/473 , H01L23/3677 , H01L23/3732 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/051 , H01L2224/05548 , H01L2224/0557 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , Y10S257/93 , H01L2924/00 , H01L2224/05599
摘要： A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.
-
公开(公告)号：US06400619B1
公开(公告)日：2002-06-04
申请号：US09841950
申请日：2001-04-25
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/24 , G11C2207/104
摘要： A new micro-cell redundancy scheme for a wide bandwidth embedded DRAM having a SRAM cache interface. For each bank of micro-cell array units comprising the eDRAM, at least one micro-cell unit is prepared as the redundancy to replace a defected micro-cell within the bank. After array testing, any defective micro-cell inside the bank is replaced with a redundancy micro-cell for that bank. A fuse bank structure implementing a look-up table is established for recording each redundant micro-cell address and its corresponding repaired micro-cell address. In order to allow simultaneous multi-bank operation, the redundant micro-cells may only replace the defective micro-cells within the same bank. When reading data from eDRAM, or writing data to eDRAM, the micro-cell array address is checked against the look-up table to determine whether that data is to be read from or written to the original micro-cell, or the redundant micro-cell. The micro-cell redundancy scheme is a flexible and reliable method for high-performance eDRAM applications.
摘要翻译： 一种用于具有SRAM缓存接口的宽带宽嵌入式DRAM的新型微小区冗余方案。 对于包括eDRAM的每个微单元阵列单元组，至少一个微单元单元被准备为冗余以替代该单元内的缺陷微单元。 在阵列测试之后，银行内的任何有缺陷的微单元被该银行的冗余微单元替代。 建立实现查找表的熔丝库结构，用于记录每个冗余微小区地址及其对应的修复的微小区地址。 为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。 当从eDRAM读取数据或将数据写入eDRAM时，将针对查找表检查微单元阵列地址，以确定该数据是从原始微单元读取还是写入原始微单元， 细胞。 微单元冗余方案是高性能eDRAM应用的灵活可靠的方法。
-
8.发明授权Method for fabricating semiconductor devices with different properties using maskless process 失效使用无掩模工艺制造具有不同特性的半导体器件的方法公开(公告)号：US06355531B1
公开(公告)日：2002-03-12
申请号：US09634225
申请日：2000-08-09
IPC分类号： H01L218236
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/82385 , Y10S438/981
摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.
摘要翻译： 提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。 该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得 第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第 除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层 在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。 半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。
-
9.发明授权公开(公告)号：US07052937B2
公开(公告)日：2006-05-30
申请号：US10429758
申请日：2003-05-05
IPC分类号： H01L21/44
CPC分类号： H01L21/76264 , H01L21/76283 , H01L23/3677 , H01L23/3732 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.
-
10.发明授权公开(公告)号：US07029956B2
公开(公告)日：2006-04-18
申请号：US10666972
申请日：2003-09-19
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L21/332
CPC分类号： H01L27/1027 , H01L21/8213 , H01L27/0605 , Y10S438/931
摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.
-
-
-
-
-
-
-
-
-
搜索结果
84 条记录 (耗时 0.039 秒)
