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    Lithographic photomask and method of manufacture to improve photomask test measurement
    1.
    发明授权
    Lithographic photomask and method of manufacture to improve photomask test measurement 失效
    平版印刷光掩模和制造方法以改进光掩模测试测量

    公开(公告)号：US06974652B1

    公开(公告)日：2005-12-13

    申请号：US10699748

    申请日：2003-11-03

    申请人： Todd P. Lukanc ,  Luigi Capodieci ,  Bhanwar Singh ,  Christopher A. Spence

    发明人： Todd P. Lukanc ,  Luigi Capodieci ,  Bhanwar Singh ,  Christopher A. Spence

    IPC分类号： G01F9/00 ,  G03F1/00 ,  G03F1/08 ,  G03F1/14

    CPC分类号： G03F1/40 ,  G03F1/58 ,  G03F1/86

    摘要： A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.

    摘要翻译： 公开了用于光刻工艺的光掩模和制造光掩模的方法。 可以提供包括衬底，设置在衬底上的牺牲导电层和设置在牺牲导电层上方的辐射屏蔽层的掩模坯料。 然后从辐射屏蔽层形成结构以限定图案。 使用测量工具测量与结构相关的参数，并且在测量期间，牺牲导电层提供导电平面以消散由测量工具传递到掩模的电荷。

    Microdevice having non-linear structural component and method of fabrication
    4.
    发明授权
    Microdevice having non-linear structural component and method of fabrication 有权
    具有非线性结构部件和制造方法的微器件

    公开(公告)号：US06995433B1

    公开(公告)日：2006-02-07

    申请号：US10791250

    申请日：2004-03-02

    申请人： Todd P. Lukanc ,  Sarah N. McGowan ,  Luigi Capodieci ,  Bhanwar Singh ,  Joerg Reiss

    发明人： Todd P. Lukanc ,  Sarah N. McGowan ,  Luigi Capodieci ,  Bhanwar Singh ,  Joerg Reiss

    IPC分类号： H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/7835 ,  H01L21/32139 ,  H01L29/4238 ,  H01L29/66659

    摘要： A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.

    摘要翻译： 公开了一种用于形成集成电路的一部分的微型器件及其制造方法。 微器件可以包括第一导电区域和介于其之间的沟道区域的第二导电区域。 微电极具有设置在沟道区域上并由至少一个电介质层分离的沟道区域控制部件。 通道区域控制部件具有从用作沟道区域控制部件的蚀刻掩模的光致抗蚀剂特征的非线性结构特性导出的非线性结构特性。

    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results
    5.
    发明授权
    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results 有权
    计量配方生成方法和系统，设计，模拟和计量结果的审查和分析

    公开(公告)号：US07207017B1

    公开(公告)日：2007-04-17

    申请号：US10865047

    申请日：2004-06-10

    申请人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    发明人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

    摘要翻译： 生成计量配方的方法包括识别设备布局内的感兴趣区域。 可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。 裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。 根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。

    Predefined critical spaces in IC patterning to reduce line end pull back
    8.
    发明授权
    Predefined critical spaces in IC patterning to reduce line end pull back 有权
    IC图案化中预定的关键空间，以减少线端拉回

    公开(公告)号：US07071085B1

    公开(公告)日：2006-07-04

    申请号：US10852876

    申请日：2004-05-25

    申请人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    发明人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    IPC分类号： H01L21/475

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  Y10S438/947

    摘要： The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

    摘要翻译： 本发明包括一种制造这种设备的装置和方法，包括以下步骤：形成待图案化的层，在待图案化的层上形成感光层，使光敏层形成图案，形成包括水平线和垂直线 将图案转移到待图案化的层上，在图案上形成第二感光层，图案化第二感光层以形成包括在水平线和垂直线之间对准的空间的第二图案，并且转印 第二图案到要被图案化的层以形成包括水平线和在其间具有空间的垂直线的第三图案，该空间包括在光刻的分辨率极限下可实现的宽度尺寸。

    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
    10.
    发明授权
    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
    通过考虑布局交互以及额外的可制造性边际来优化集成电路布局

    公开(公告)号：US07313769B1

    公开(公告)日：2007-12-25

    申请号：US10790381

    申请日：2004-03-01

    申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

    摘要翻译： 产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。 基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。 可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。