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    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF
    1.
    发明公开
    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF 审中-公开

    公开(公告)号：US20240231623A9

    公开(公告)日：2024-07-11

    申请号：US18049303

    申请日：2022-10-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chih CHIEN ,  Cheng-Lin SUNG ,  Hsiang-Lan LUNG

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

    Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

    METHOD FOR OPERATING MEMORY DEVICE AND MEMORY DEVICE
    2.
    发明公开
    METHOD FOR OPERATING MEMORY DEVICE AND MEMORY DEVICE 审中-公开

    公开(公告)号：US20240184464A1

    公开(公告)日：2024-06-06

    申请号：US18302942

    申请日：2023-04-19

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan LIN ,  Hsiang-Lan LUNG ,  Cheng-Lin SUNG

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A method for operating a memory device is provided. The method includes following steps. First, a priority of a refresh operation and a priority of an inference operation for at least a portion of a memory array of the memory device are determined. The refresh operation and the inference operation are performed according to a determination result of the priority of the refresh operation and the priority of the inference operation. If the priority of the refresh operation is lower than the priority of inference operation, perform the inference operation in the at least a portion, and perform the refresh operation after performing the inference operation. If the priority of the refresh operation is higher than the priority of inference operation, perform the refresh operation in the at least a portion, and perform the inference operation after performing the refresh operation.

    SPIKING NEURAL NETWORKS CIRCUIT AND OPERATION METHOD THEREOF
    4.
    发明申请
    SPIKING NEURAL NETWORKS CIRCUIT AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20210241081A1

    公开(公告)日：2021-08-05

    申请号：US16872404

    申请日：2020-05-12

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Cheng-Lin SUNG ,  Teng-Hao YEH

    IPC: G06N3/063 ,  G11C11/54 ,  G11C16/24 ,  G11C16/26 ,  G06N3/04

    Abstract: A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse.

    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF
    5.
    发明公开
    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF 审中-公开

    公开(公告)号：US20240134529A1

    公开(公告)日：2024-04-25

    申请号：US18049303

    申请日：2022-10-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chih CHIEN ,  Cheng-Lin SUNG ,  Hsiang-Lan LUNG

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

    Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

    SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20220254799A1

    公开(公告)日：2022-08-11

    申请号：US17495826

    申请日：2021-10-07

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hang-Ting LUE ,  Cheng-Lin SUNG ,  Wei-Chen CHEN

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

    Abstract: A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line.

    MULTI-GATE TRANSISTOR AND MEMORY DEVICE USING THE SAME
    10.
    发明申请
    MULTI-GATE TRANSISTOR AND MEMORY DEVICE USING THE SAME 有权

    公开(公告)号：US20210242347A1

    公开(公告)日：2021-08-05

    申请号：US16877518

    申请日：2020-05-19

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Cheng-Lin SUNG ,  Pei-Ying DU ,  Hang-Ting LUE

    IPC: H01L29/788 ,  H01L29/792 ,  G11C11/56

    Abstract: A multi-gate transistor includes; a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

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