公开(公告)号：US12087694B2

公开(公告)日：2024-09-10

申请号：US17683442

申请日：2022-03-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ya-Chun Tsai

IPC: H01L23/535 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a bottom isolating member and a common wall, wherein the unprocessed region extends along the first direction and has an isolating sidewall, the isolating sidewall electrically isolates the conductive layers from the unprocessed region, the staircase region is adjacent to a first side of the unprocessed region, and the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.

公开(公告)号：US20230223343A1

公开(公告)日：2023-07-13

申请号：US17574170

申请日：2022-01-12

Applicant: Macronix International Co., Ltd.

Inventor： Ya-Chun Tsai

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure. The first and second stepped structures are arranged between the first and second connection areas along a second direction perpendicular to the first direction.

公开(公告)号：US12256543B2

公开(公告)日：2025-03-18

申请号：US17669039

申请日：2022-02-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Ya-Chun Tsai

IPC: H01L29/76 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10D30/67

Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.

公开(公告)号：US12218061B2

公开(公告)日：2025-02-04

申请号：US17574170

申请日：2022-01-12

Applicant: Macronix International Co., Ltd.

Inventor： Ya-Chun Tsai

IPC: H01L23/535 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure. The first and second stepped structures are arranged between the first and second connection areas along a second direction perpendicular to the first direction.

公开(公告)号：US11903194B2

公开(公告)日：2024-02-13

申请号：US17529027

申请日：2021-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Chun Tsai

IPC: G11C5/02 ,  H10B43/10 ,  G11C16/26 ,  G11C16/08 ,  H10B41/10

CPC classification number: H10B43/10 ,  G11C16/08 ,  G11C16/26 ,  H10B41/10

Abstract: In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.

公开(公告)号：US20230255028A1

公开(公告)日：2023-08-10

申请号：US17669039

申请日：2022-02-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  Ya-Chun Tsai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/5283 ,  H01L29/42392

Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.

公开(公告)号：US20230157018A1

公开(公告)日：2023-05-18

申请号：US17529027

申请日：2021-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Chun Tsai

IPC: H01L27/11565 ,  H01L27/11519 ,  G11C16/08 ,  G11C16/26

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  G11C16/08 ,  G11C16/26

Abstract: In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.