公开(公告)号：US20220139848A1

公开(公告)日：2022-05-05

申请号：US17575789

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/367 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.

公开(公告)号：US20180233452A1

公开(公告)日：2018-08-16

申请号：US15891481

申请日：2018-02-08

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5283 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.

公开(公告)号：US20230197684A1

公开(公告)日：2023-06-22

申请号：US18170078

申请日：2023-02-16

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/3128 ,  H01L2224/16113 ,  H01L24/16 ,  H01L23/3675 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240153887A1

公开(公告)日：2024-05-09

申请号：US18403974

申请日：2024-01-04

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/00 ,  H01L23/043 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/043 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/5385 ,  H01L2224/16227

Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

公开(公告)号：US20190043771A1

公开(公告)日：2019-02-07

申请号：US16002138

申请日：2018-06-07

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

公开(公告)号：US20210175137A1

公开(公告)日：2021-06-10

申请号：US17182525

申请日：2021-02-23

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/04 ,  H01L25/18 ,  H01L23/16

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

公开(公告)号：US20200075572A1

公开(公告)日：2020-03-05

申请号：US16674298

申请日：2019-11-05

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  I-Hsuan PENG ,  Tzu-Hung LIN

IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

公开(公告)号：US20220336374A1

公开(公告)日：2022-10-20

申请号：US17810625

申请日：2022-07-04

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/043 ,  H01L23/13 ,  H01L23/538

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. A hole is formed on a surface of the substrate, wherein the hole is located within projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material, surrounding the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate, are exposed by the molding material.

公开(公告)号：US20220020726A1

公开(公告)日：2022-01-20

申请号：US17488921

申请日：2021-09-29

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

公开(公告)号：US20190043848A1

公开(公告)日：2019-02-07

申请号：US16043326

申请日：2018-07-24

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  I-Hsuan PENG ,  Tzu-Hung LIN

IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.