公开(公告)号：US20170200783A1

公开(公告)日：2017-07-13

申请号：US15469846

申请日：2017-03-27

Applicant: MediaTek Inc.

Inventor： Zheng ZENG ,  Ching-Chung KO ,  Bo-Shih HUANG

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/78 ,  H01L27/02 ,  H01L29/47

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

公开(公告)号：US20240178221A1

公开(公告)日：2024-05-30

申请号：US18502225

申请日：2023-11-06

Applicant: MEDIATEK INC.

Inventor： Shih-Chuan CHIU ,  Chia-Hsin HU ,  Zheng ZENG

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/0623 ,  H01L27/0629 ,  H01L29/7308 ,  H01L29/7851 ,  H01L29/872

Abstract: Semiconductor structures of Schottky devices are provided. An N-type well region and a P-type well region are formed over a P-type semiconductor substrate. A first active region is formed over the P-type well region, and includes a plurality of first fins. A second active region is formed over the N-type well region, and includes a plurality of second fins. A third active region is formed over the N-type well region, and includes a plurality of third fins. A plurality of electrodes are formed over the third active region. The electrodes, the first source/drain features and the second source/drain features are formed in the same level. An emitter region of a Schottky BJT is formed by the electrodes, a base region of the Schottky BJT is formed by the N-type well region, and a collector region of the Schottky BJT is formed by the P-type semiconductor substrate.

公开(公告)号：US20220013441A1

公开(公告)日：2022-01-13

申请号：US17363459

申请日：2021-06-30

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih LIU ,  Zheng ZENG ,  Che-Hung KUO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US20240290780A1

公开(公告)日：2024-08-29

申请号：US18413264

申请日：2024-01-16

Applicant: MEDIATEK INC.

Inventor： Zheng ZENG ,  Chia-Hsin HU ,  Chen-Ting LENG

IPC: H01L27/06 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/94

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, first and second well regions, first and second gate-all-around (GAA) field-effect transistor devices and a first dielectric layer. The first and second well regions are arranged in the semiconductor substrate and separated from each other. Top and bottom surfaces of the first and second well regions are aligned with top and bottom surfaces of the semiconductor substrate. The first and second GAA field-effect transistor devices are formed over the first and second well regions. A first gate structure of the first GAA field-effect transistor device is electrically connected to a power supply terminal. The first epitaxial source/drain features of the first GAA field-effect transistor are electrically connected to the second gate structure of the second GAA field-effect transistor. The second epitaxial source/drain features of the second GAA field-effect transistor are electrically connected to a ground terminal.

公开(公告)号：US20140203368A1

公开(公告)日：2014-07-24

申请号：US14108559

申请日：2013-12-17

Applicant: MediaTek Inc.

Inventor： Zheng ZENG ,  Ching-Chung KO ,  Bo-Shih HUANG

IPC: H01L27/02

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.

Abstract translation: 本发明提供一种静电放电（ESD）保护装置。 ESD保护器件包括具有有源区的半导体衬底。 在有源区中形成具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区形成在第一阱区中。 第一金属触点设置在第一掺杂区域上。 第二金属触点设置在有源区上，连接到第一阱区。 第一金属触点和第二金属触点被设置在第一阱区域上的多晶型图案或绝缘层图案分开。

公开(公告)号：US20240128262A1

公开(公告)日：2024-04-18

申请号：US18460839

申请日：2023-09-05

Applicant: MEDIATEK INC.

Inventor： Shih-Chuan CHIU ,  Chia-Hsin HU ,  Zheng ZENG

IPC: H01L27/082

CPC classification number: H01L27/082 ,  H01L27/0823

Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.

公开(公告)号：US20240038755A1

公开(公告)日：2024-02-01

申请号：US18344126

申请日：2023-06-29

Applicant: MEDIATEK INC.

Inventor： Chia-Hsin HU ,  Wei-Chieh TSENG ,  Zheng ZENG

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L29/785 ,  H01L27/0924 ,  H01L27/0922 ,  H01L29/66545

Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.

公开(公告)号：US20240014295A1

公开(公告)日：2024-01-11

申请号：US18327287

申请日：2023-06-01

Applicant: MEDIATEK INC.

Inventor： Shih-Chuan CHIU ,  Chia-Hsin HU ,  Zheng ZENG

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/0821

Abstract: Semiconductor structures of bipolar junction transistor (BJT) are provided. A first active region of a collection region is formed over a first P-type well region. Second and third active regions of a base region are formed over an N-type well region. A fourth active region of an emitter region is formed over a second P-type well region. The first active region includes a plurality of first fins and a plurality of first source/drain features epitaxially grown on the first fins. Each of the second and third active regions includes a plurality of second fins and a plurality of second source/drain features epitaxially grown on the second fins. The fourth active region includes a plurality of third fins and a plurality of third source/drain features epitaxially grown on the third fins. The second and third active regions are disposed on opposite sides of the fourth active region.

公开(公告)号：US20230317580A1

公开(公告)日：2023-10-05

申请号：US18329721

申请日：2023-06-06

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih LIU ,  Zheng ZENG ,  Che-Hung KUO

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/5389 ,  H01L23/5385 ,  H01L25/105 ,  H01L23/481 ,  H01L25/0657 ,  H01L23/3128

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US20200373428A1

公开(公告)日：2020-11-26

申请号：US16853889

申请日：2020-04-21

Applicant: MEDIATEK INC.

Inventor： Jing-Chyi LIAO ,  Ching-Chung KO ,  Zheng ZENG

IPC: H01L29/78

Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.