公开(公告)号：US10459871B2

公开(公告)日：2019-10-29

申请号：US15703736

申请日：2017-09-13

Applicant: Micron Technology, Inc.

Inventor： Akinori Funahashi ,  Chikara Kondo

IPC: G06F13/12 ,  G06F13/42 ,  G11C8/18 ,  G11C5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

公开(公告)号：US20180277175A1

公开(公告)日：2018-09-27

申请号：US15468742

申请日：2017-03-24

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Akinori Funahashi

IPC: G11C7/10 ,  G06F13/40 ,  H03M13/29 ,  G11C29/12 ,  G11C29/36

CPC classification number: G06F13/4022 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/36 ,  G11C2029/1202 ,  H03M13/29

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.

公开(公告)号：US10915487B2

公开(公告)日：2021-02-09

申请号：US16553552

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Akinori Funahashi ,  Chikara Kondo

IPC: G06F13/42 ,  G11C8/18 ,  G11C5/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/02

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

公开(公告)号：US20190384739A1

公开(公告)日：2019-12-19

申请号：US16553552

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Akinori Funahashi ,  Chikara Kondo

IPC: G06F13/42 ,  G06F13/16 ,  G11C5/06 ,  G11C8/18

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.

公开(公告)号：US20190079893A1

公开(公告)日：2019-03-14

申请号：US15703736

申请日：2017-09-13

Applicant: Micron Technology, Inc.

Inventor： Akinori Funahashi ,  Chikara Kondo

IPC: G06F13/42 ,  G06F13/16 ,  G11C5/06 ,  G11C8/18

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G11C5/06 ,  G11C5/066 ,  G11C7/02 ,  G11C7/1048 ,  G11C8/18

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.

公开(公告)号：US20190034370A1

公开(公告)日：2019-01-31

申请号：US16150505

申请日：2018-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Akinori Funahashi

IPC: G06F13/40 ,  G11C29/36 ,  G11C29/12 ,  G11C7/10 ,  H03M13/29

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.

公开(公告)号：US10146719B2

公开(公告)日：2018-12-04

申请号：US15468742

申请日：2017-03-24

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Akinori Funahashi

IPC: G06F13/40 ,  G11C7/10 ,  H03M13/29 ,  G11C29/12 ,  G11C29/36

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.