公开(公告)号：US08872310B2

公开(公告)日：2014-10-28

申请号：US13713210

申请日：2012-12-13

Applicant: Micron Technology, Inc.

Inventor： Chad A. Cobbley ,  Jonathon G. Greenwood

IPC: H01L29/06 ,  H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/12 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/19043 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed.

Abstract translation: 半导体器件的导电通孔包括延伸到制造衬底的有源表面的相对小的直径部分和延伸到制造衬底的背侧的对应的相对较大的直径部分。 这种类型的导电通孔可以通过在BEOL处理之前或期间形成相对较小的直径部分来制造，而每个导电通孔的大直径部分可以在BEOL处理完成之后制造。 还公开了包括具有这种导电通孔的一个或多个半导体器件的电子器件。

公开(公告)号：US20130187289A1

公开(公告)日：2013-07-25

申请号：US13713210

申请日：2012-12-13

Applicant: Micron Technology, Inc.

Inventor： Chad A. Cobbley ,  Jonathon G. Greenwood

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/12 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/19043 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed.

Abstract translation: 半导体器件的导电通孔包括延伸到制造衬底的有源表面的相对小的直径部分和延伸到制造衬底的背侧的对应的相对较大的直径部分。 这种类型的导电通孔可以通过在BEOL处理之前或期间形成相对较小的直径部分来制造，而每个导电通孔的大直径部分可以在BEOL处理完成之后制造。 还公开了包括具有这种导电通孔的一个或多个半导体器件的电子器件。

公开(公告)号：US09559087B2

公开(公告)日：2017-01-31

申请号：US14102310

申请日：2013-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Todd O. Bolken ,  Chad A. Cobbley

IPC: H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract translation: 制造多器件组件的技术。 具体地，涉及用于制造包括至少一个I / C模块和多芯片封装的堆叠封装的技术。 多芯片封装包括耦合到载体的多个集成电路芯片。 骰子被封装，使得导电元件通过密封剂暴露。 导电元件电耦合到芯片。 I / C模块包括具有设置在其上的多个集成电路芯片的插入器。 I / C模块的裸片通过焊丝电耦合到插入器。 插入器被配置为使得通孔与多芯片封装上的导电元件对准。 多芯片封装和I / C模块可以单独制造，然后耦合在一起以形成堆叠封装。

公开(公告)号：US20140099753A1

公开(公告)日：2014-04-10

申请号：US14102310

申请日：2013-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Todd O. Bolken ,  Chad A. Cobbley

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract translation: 制造多器件组件的技术。 具体地，涉及用于制造包括至少一个I / C模块和多芯片封装的堆叠封装的技术。 多芯片封装包括耦合到载体的多个集成电路芯片。 骰子被封装，使得导电元件通过密封剂暴露。 导电元件电耦合到芯片。 I / C模块包括具有设置在其上的多个集成电路芯片的插入器。 I / C模块的裸片通过焊丝电耦合到插入器。 插入器被配置为使得通孔与多芯片封装上的导电元件对准。 多芯片封装和I / C模块可以单独制造，然后耦合在一起以形成堆叠封装。