公开(公告)号：US20220230960A1

公开(公告)日：2022-07-21

申请号：US17658404

申请日：2022-04-07

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US20210151375A1

公开(公告)日：2021-05-20

申请号：US17134930

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20180204799A1

公开(公告)日：2018-07-19

申请号：US15916575

申请日：2018-03-09

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11517 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US09082772B2

公开(公告)日：2015-07-14

申请号：US14085361

申请日：2013-11-20

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L29/76 ,  H01L29/788 ,  H01L23/552 ,  H01L23/535 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US11302634B2

公开(公告)日：2022-04-12

申请号：US16790148

申请日：2020-02-13

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US10290581B2

公开(公告)日：2019-05-14

申请号：US15916575

申请日：2018-03-09

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11517 ,  H01L27/11548

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20250038109A1

公开(公告)日：2025-01-30

申请号：US18916144

申请日：2024-10-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US11430734B2

公开(公告)日：2022-08-30

申请号：US17134930

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11517 ,  H01L27/11548

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US09941209B2

公开(公告)日：2018-04-10

申请号：US15068329

申请日：2016-03-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11517

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US12125786B2

公开(公告)日：2024-10-22

申请号：US17819004

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B43/50 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.