公开(公告)号：US11302653B2

公开(公告)日：2022-04-12

申请号：US16993860

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US10748857B2

公开(公告)日：2020-08-18

申请号：US16127769

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US20190385967A1

公开(公告)日：2019-12-19

申请号：US16550045

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  G06F17/50 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

公开(公告)号：US20190189576A1

公开(公告)日：2019-06-20

申请号：US16276533

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US20190088637A1

公开(公告)日：2019-03-21

申请号：US15711937

申请日：2017-09-21

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L25/50 ,  H01L21/02021 ,  H01L21/02076 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/71 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US10896886B2

公开(公告)日：2021-01-19

申请号：US16276533

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US10403618B2

公开(公告)日：2019-09-03

申请号：US15711937

申请日：2017-09-21

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US20190198377A1

公开(公告)日：2019-06-27

申请号：US15855622

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  B32B43/00

Abstract: Systems and methods for debonding a carrier from a semiconductor device are disclosed herein. In one embodiment, a system for debonding a carrier from a semiconductor device includes a support member positioned to carry the semiconductor device and a fluid delivery device having an exit positioned to direct a fluid toward an adhesive layer between the carrier and the semiconductor device. The fluid directed from the fluid delivery device initiates debonding of the carrier from the semiconductor device by weakening or loosening at least a portion of the adhesive. The system further includes a liftoff device configured to releasably engage the carrier and apply a debonding force to the carrier to complete debonding of the carrier from the semiconductor device.

公开(公告)号：US20190157112A1

公开(公告)日：2019-05-23

申请号：US16009119

申请日：2018-06-14

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US10002840B1

公开(公告)日：2018-06-19

申请号：US15672006

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.