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公开(公告)号：US09921898B1
公开(公告)日：2018-03-20
申请号：US15390833
申请日：2016-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, Jr. , Yun Li , Kishore Kumar Muchherla
CPC classification number: G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079
Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.
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公开(公告)号：US11163572B2
公开(公告)日：2021-11-02
申请号：US14172806
申请日：2014-02-04
Applicant: Micron Technology, Inc.
Inventor： Umberto Siciliani , Tommaso Vali , Walter Di-Francesco , Violante Moschiano , Andrea Smaniotto
IPC: G06F9/32
Abstract: Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.
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公开(公告)号：US10818363B1
公开(公告)日：2020-10-27
申请号：US16414897
申请日：2019-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gianfranco Valeri , Violante Moschiano , Walter Di-Francesco
Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.
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公开(公告)号：US20180196705A1
公开(公告)日：2018-07-12
申请号：US15911490
申请日：2018-03-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, JR. , Yun Li , Kishore Kumar Muchherla
CPC classification number: G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079
Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
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公开(公告)号：US11842774B2
公开(公告)日：2023-12-12
申请号：US17583537
申请日：2022-01-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gianfranco Valeri , Violante Moschiano , Walter Di-Francesco
CPC classification number: G11C16/28 , G06F11/1008 , G11C13/004 , G11C16/107
Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.
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Patent Agency Ranking
公开(公告)号：US10942796B2
公开(公告)日：2021-03-09
申请号：US16544190
申请日：2019-08-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, Jr. , Yun Li , Kishore Kumar Muchherla
IPC: G11C11/34 , G06F11/07 , G06F3/06 , G06F11/10 , G11C11/56 , G11C16/10 , G11C16/22 , G11C16/30 , G11C16/34 , G11C5/14
Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
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公开(公告)号：US20190073251A1
公开(公告)日：2019-03-07
申请号：US16178963
申请日：2018-11-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, JR. , Yun Li , Kishore Kumar Muchherla
CPC classification number: G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079 , G06F11/1068 , G11C5/144 , G11C11/5628 , G11C16/10 , G11C16/225 , G11C16/30 , G11C16/3459
Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
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公开(公告)号：US20150220344A1
公开(公告)日：2015-08-06
申请号：US14172806
申请日：2014-02-04
Applicant: Micron Technology, Inc.
Inventor： Umberto Siciliani , Tommaso Vali , Walter Di-Francesco , Violante Moschiano , Andrea Smaniotto
Abstract: Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.
Abstract translation: 描述了存储器系统和存储器控制方法。 根据一个方面，一种存储器系统包括单独配置为存储数据的多个存储器单元，被配置为存储根据第一指令序列排序的多个第一可执行指令的程序存储器和被排序的多个第二可执行指令 根据第二指令序列，替代电路被配置为用替代可执行指令来替换第一可执行指令之一，以及控制单元，被配置为执行第一和第二可执行指令以控制相对于存储器的数据的读取和写入 其中，所述控制单元被配置为根据所述第一指令序列执行所述第一可执行指令，以在执行所述第一可执行指令之后执行所述替代可执行指令，并且根据所述第二指令序列执行所述第二可执行指令作为 的结果 执行替代可执行指令。
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公开(公告)号：US20220148661A1
公开(公告)日：2022-05-12
申请号：US17583537
申请日：2022-01-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gianfranco Valeri , Violante Moschiano , Walter Di-Francesco
Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.
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公开(公告)号：US11270774B2
公开(公告)日：2022-03-08
申请号：US17079594
申请日：2020-10-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gianfranco Valeri , Violante Moschiano , Walter Di-Francesco
Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.
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