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公开(公告)号：US10367522B2
公开(公告)日：2019-07-30
申请号：US15819475
申请日：2017-11-21
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.
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公开(公告)号：US20190356329A1
公开(公告)日：2019-11-21
申请号：US16525066
申请日：2019-07-29
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.
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Patent Agency Ranking
公开(公告)号：US10020818B1
公开(公告)日：2018-07-10
申请号：US15470805
申请日：2017-03-27
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
CPC classification number: H03M3/436 , H03M1/12 , H03M3/022 , H03M3/30 , H03M3/434 , H03M3/452 , H03M3/454 , H03M3/464 , H04B1/40 , H04L1/006
Abstract: An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k−1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).
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公开(公告)号：US10812087B2
公开(公告)日：2020-10-20
申请号：US16703580
申请日：2019-12-04
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
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公开(公告)号：US20200106448A1
公开(公告)日：2020-04-02
申请号：US16703580
申请日：2019-12-04
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
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公开(公告)号：US20180145700A1
公开(公告)日：2018-05-24
申请号：US15819475
申请日：2017-11-21
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
CPC classification number: H03M3/39 , H03F1/0227 , H03F3/19 , H03F3/2171 , H03F3/2175 , H03F3/245 , H03F2200/102 , H03F2200/171 , H03F2200/451 , H03M7/3004
Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.
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公开(公告)号：US10530372B1
公开(公告)日：2020-01-07
申请号：US15470616
申请日：2017-03-27
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
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