公开(公告)号：US09449821B2

公开(公告)日：2016-09-20

申请号：US14333802

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  An Chyi Wei

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/0276 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32137 ,  H01L27/11551 ,  H01L27/11578

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract translation: 集成电路中的高纵横比沟槽由复合材料制成，沟槽边界具有铅笔状蚀刻轮廓。 制造方法减少了沟槽边界与制造过程中应用的流体之间的表面张力，从而避免了图案弯曲，弯曲和塌陷。 此外，该方法还有助于用合适的选定材料填充沟槽。

公开(公告)号：US20160020211A1

公开(公告)日：2016-01-21

申请号：US14333802

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  An Chyi Wei

IPC: H01L27/105 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/0276 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32137 ,  H01L27/11551 ,  H01L27/11578

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract translation: 集成电路中的高纵横比沟槽由复合材料制成，沟槽边界具有铅笔状蚀刻轮廓。 制造方法减少了沟槽边界与制造过程中应用的流体之间的表面张力，从而避免了图案弯曲，弯曲和塌陷。 此外，该方法还有助于用合适的选定材料填充沟槽。

公开(公告)号：US20160020119A1

公开(公告)日：2016-01-21

申请号：US14333113

申请日：2014-07-16

Applicant: Macronix International Co., Ltd.

Inventor： Sheng-Yuan Chang ,  An Chyi Wei

IPC: H01L21/3213 ,  H01L27/105 ,  H01L23/532 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/32137 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11582

Abstract: A semiconductor stack includes a carbon doped/implanted stop layer that reacts with etching plasma to form polymers that maintain bottom etched critical dimension (ECD) and avoid excess recess depth when over-etching in high-aspect-ratio structures.

Abstract translation: 半导体堆叠包括碳掺杂/注入的停止层，其与蚀刻等离子体反应以形成保持底部蚀刻临界尺寸（ECD）并且在高纵横比结构中过蚀刻时避免过多的凹陷深度的聚合物。

公开(公告)号：US09349746B1

公开(公告)日：2016-05-24

申请号：US14594768

申请日：2015-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang ,  Nan-Tsu Lian ,  An Chyi Wei ,  Sheng-Yuan Chang ,  Kuang-Chao Chen

IPC: H01L29/51 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/511 ,  H01L29/518

Abstract: Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Abstract translation: 本示例实施例一般涉及用于制造半导体器件的方法，包括在衬底上形成交替的绝缘和导电层的初始叠层，识别用于初始堆叠的多个位线位置和字线位置，包括第一位线位置和 第一字线位置，并且从初始堆叠形成第一位线位置中的位线的垂直布置，位线的垂直布置具有相对的侧壁。 该方法还包括通过在相对侧壁的选定部分上形成薄导电层来形成字线，相对侧壁的选定部分是第一字线位置内的部分。 形成字线还包括沉积与每个薄导电层相邻的导电材料，沉积的导电材料与薄导电层直接接触。