公开(公告)号：US09349746B1

公开(公告)日：2016-05-24

申请号：US14594768

申请日：2015-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang ,  Nan-Tsu Lian ,  An Chyi Wei ,  Sheng-Yuan Chang ,  Kuang-Chao Chen

IPC: H01L29/51 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/511 ,  H01L29/518

Abstract: Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Abstract translation: 本示例实施例一般涉及用于制造半导体器件的方法，包括在衬底上形成交替的绝缘和导电层的初始叠层，识别用于初始堆叠的多个位线位置和字线位置，包括第一位线位置和 第一字线位置，并且从初始堆叠形成第一位线位置中的位线的垂直布置，位线的垂直布置具有相对的侧壁。 该方法还包括通过在相对侧壁的选定部分上形成薄导电层来形成字线，相对侧壁的选定部分是第一字线位置内的部分。 形成字线还包括沉积与每个薄导电层相邻的导电材料，沉积的导电材料与薄导电层直接接触。

公开(公告)号：US20160020119A1

公开(公告)日：2016-01-21

申请号：US14333113

申请日：2014-07-16

Applicant: Macronix International Co., Ltd.

Inventor： Sheng-Yuan Chang ,  An Chyi Wei

IPC: H01L21/3213 ,  H01L27/105 ,  H01L23/532 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/32137 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11582

Abstract: A semiconductor stack includes a carbon doped/implanted stop layer that reacts with etching plasma to form polymers that maintain bottom etched critical dimension (ECD) and avoid excess recess depth when over-etching in high-aspect-ratio structures.

Abstract translation: 半导体堆叠包括碳掺杂/注入的停止层，其与蚀刻等离子体反应以形成保持底部蚀刻临界尺寸（ECD）并且在高纵横比结构中过蚀刻时避免过多的凹陷深度的聚合物。

公开(公告)号：US20160172294A1

公开(公告)日：2016-06-16

申请号：US14571686

申请日：2014-12-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Sheng-Yuan Chang ,  An-Chyi Wei ,  Nan-Tsu Lian ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high aspect ratio structure is provided. The high aspect ratio structure includes a substrate, a plurality of stack structures, and a plurality of support structures. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of first material layers and a plurality of second material layers. The second material layers and the first material layers are disposed alternately. The support structures are respectively disposed between the substrate and the stack structures, wherein each of the support structures has a concave-convex surface.

Abstract translation: 提供了高纵横比结构。 高纵横比结构包括基板，多个堆叠结构和多个支撑结构。 堆叠结构设置在衬底上，并且在相邻的两个堆叠结构之间形成沟槽。 每个堆叠结构包括多个第一材料层和多个第二材料层。 第二材料层和第一材料层交替设置。 支撑结构分别设置在基板和堆叠结构之间，其中每个支撑结构具有凹凸表面。