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    SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE
    4.
    发明申请
    SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE 有权
    具有优化的DOPANT轮廓的半导体晶体管器件

    公开(公告)号：US20130113041A1

    公开(公告)日：2013-05-09

    申请号：US13288201

    申请日：2011-11-03

    申请人： Chia-Wen LIU ,  Tsung-Hsing Yu ,  Dhanyakumar Mahaveer Sathaiya ,  Wei-Hao Wu ,  Ken-Ichi Goto ,  Tzer-Min Shen ,  Zhiqiang Wu

    发明人： Chia-Wen LIU ,  Tsung-Hsing Yu ,  Dhanyakumar Mahaveer Sathaiya ,  Wei-Hao Wu ,  Ken-Ichi Goto ,  Tzer-Min Shen ,  Zhiqiang Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66492 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/931

    摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

    摘要翻译： 提供了一种用于在半导体器件中形成晶体管的晶体管和方法。 该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。 使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。 如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。 掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

    Multi-gate semiconductor devices
    5.
    发明授权
    Multi-gate semiconductor devices 有权
    多栅极半导体器件

    公开(公告)号：US08987824B2

    公开(公告)日：2015-03-24

    申请号：US13301873

    申请日：2011-11-22

    申请人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

    摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

    摘要翻译： 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

    Input buffer structure with single gate oxide
    9.
    发明申请
    Input buffer structure with single gate oxide 有权
    具有单栅极氧化物的输入缓冲结构

    公开(公告)号：US20050270079A1

    公开(公告)日：2005-12-08

    申请号：US10859726

    申请日：2004-06-03

    申请人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

    发明人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

    IPC分类号： H03K5/153 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

    CPC分类号： H03K19/018521 ,  H03K19/0027

    摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

    摘要翻译： 提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。 缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。 逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。 反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。 调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。 缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。