公开(公告)号：US08593307B2

公开(公告)日：2013-11-26

申请号：US13364787

申请日：2012-02-02

申请人： Man-keun Seo ,  Jun-jin Kong ,  Hong-rak Son ,  Kyoung-Lae Cho ,  Je-hyuck Song ,  Kwang-gu Lee

发明人： Man-keun Seo ,  Jun-jin Kong ,  Hong-rak Son ,  Kyoung-Lae Cho ,  Je-hyuck Song ,  Kwang-gu Lee

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

摘要翻译： 至少一个示例性实施例公开了一种在存储设备中压缩数据的方法。 该方法包括使用指示接收数据中的符号的出现次数与码字长度之间的关系的第一表来确定符号的码字长度，确定具有用于符号的码字长度的码字，以及生成 接收到的数据，生成包括将符号转换成码字。

公开(公告)号：US20110320689A1

公开(公告)日：2011-12-29

申请号：US13159075

申请日：2011-06-13

申请人： Kyoung Lae Cho ,  Jun-jin Kong ,  Hong-rak Son ,  Seong-hyeong Choi

发明人： Kyoung Lae Cho ,  Jun-jin Kong ,  Hong-rak Son ,  Seong-hyeong Choi

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： Methods of operating integrated circuit devices include updating a mapping table with physical address information by reading forward link information from a plurality of spare sectors in a corresponding plurality of pages within a nonvolatile memory device and then writing mapping table information derived from the forward link information into the mapping table. This forward link information may be configured as absolute address information (e.g., next physical address) and/or relative address information (e.g., change in physical address). This updating of the mapping table may include updating a mapping table within a volatile memory, in response to a resumption of power within the integrated circuit device. This resumption of power may follow a power failure during which the contents of the volatile memory are lost.

摘要翻译： 操作集成电路设备的方法包括：通过从非易失性存储器件内的相应多个页面中的多个备用扇区读取前向链路信息，然后将从前向链路信息导出的映射表信息写入到 映射表。 该前向链路信息可以被配置为绝对地址信息（例如，下一个物理地址）和/或相对地址信息（例如，物理地址的改变）。 映射表的这种更新可以包括响应于集成电路设备内的恢复功率而更新易失性存储器内的映射表。 这种恢复电源可能会在易失性存储器的内容丢失的情况下发生电源故障。

公开(公告)号：US10127978B2

公开(公告)日：2018-11-13

申请号：US14968016

申请日：2015-12-14

申请人： Eun-chu Oh ,  Pil-sang Yoon ,  Jun-jin Kong ,  Hong-rak Son

发明人： Eun-chu Oh ,  Pil-sang Yoon ,  Jun-jin Kong ,  Hong-rak Son

IPC分类号： G11C13/00 ,  H03M13/05 ,  H03M13/27 ,  G06F12/00 ,  G11C8/06 ,  G06F11/10

摘要： A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

公开(公告)号：US09128812B2

公开(公告)日：2015-09-08

申请号：US13610917

申请日：2012-09-12

申请人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

发明人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

摘要： A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to determine a read voltage level compensation value corresponding to a difference between the number of the first state values of the sample data written to the memory and the number of the first state values of the read data read from the memory.

摘要翻译： 半导体存储系统包括：差分确定电路，被配置为确定写入存储器的采样数据的第一状态值的​​数量与从存储器读取的读取数据的第一状态值的​​数量之间的差; 以及补偿值确定电路，被配置为确定对应于写入存储器的采样数据的第一状态值的​​数量与从该存储器读取的读取数据的第一状态值的​​数量之间的差对应的读取电压电平补偿值 记忆。

公开(公告)号：US20120221772A1

公开(公告)日：2012-08-30

申请号：US13404625

申请日：2012-02-24

申请人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

发明人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

IPC分类号： G06F12/00

CPC分类号： G06F13/1668

摘要： A semiconductor memory system can include a memory device having a memory cell array that includes a plurality of memory cells. A memory controller can be configured to perform domain transformation on data written to and/or read from the plurality of memory cells to provide domain-transformed data and configured to perform signal processing on the domain-transformed data to output processed data or a control signal.

摘要翻译： 半导体存储器系统可以包括具有包括多个存储单元的存储单元阵列的存储器件。 存储器控制器可以被配置为对从多个存储器单元写入和/或从多个存储器单元读取的数据执行域变换以提供域变换的数据并且被配置为对域变换的数据执行信号处理以输出处理的数据或控制信号 。

公开(公告)号：US08817545B2

公开(公告)日：2014-08-26

申请号：US13404625

申请日：2012-02-24

申请人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

发明人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

IPC分类号： G11C11/34

CPC分类号： G06F13/1668

摘要： A semiconductor memory system can include a memory device having a memory cell array that includes a plurality of memory cells. A memory controller can be configured to perform domain transformation on data written to and/or read from the plurality of memory cells to provide domain-transformed data and configured to perform signal processing on the domain-transformed data to output processed data or a control signal.

摘要翻译： 半导体存储器系统可以包括具有包括多个存储单元的存储单元阵列的存储器件。 存储器控制器可以被配置为对从多个存储器单元写入和/或从多个存储器单元读取的数据执行域变换以提供域变换的数据并且被配置为对域变换的数据执行信号处理以输出处理的数据或控制信号 。

公开(公告)号：US08218363B2

公开(公告)日：2012-07-10

申请号：US12697542

申请日：2010-02-01

申请人： Jaehong Kim ,  Hong-rak Son ,  Jun-jin Kong ,  Yoo-cheol Shin

发明人： Jaehong Kim ,  Hong-rak Son ,  Jun-jin Kong ,  Yoo-cheol Shin

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5621

摘要： Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states.

摘要翻译： 公开了多级闪存和编程/读取闪存的方法。 多级闪速存储装置包括：状态检测器，被配置为检测目标存储单元是否被编程为擦除状态;以及控制逻辑单元，控制施加到与目标存储器单元相邻的相邻存储单元的编程电压，并且为 被编程为多个标准程序状态之一，使得相邻存储器单元被编程为与多个标准程序状态之一不同的多个校正程序状态中的对应的一个。

公开(公告)号：US07606336B2

公开(公告)日：2009-10-20

申请号：US11342566

申请日：2006-01-31

申请人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

发明人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

IPC分类号： H04L27/06

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/6597

摘要： An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.

摘要翻译： 提供了一种用于解码模拟信号的模拟维特比解码器，其包括多个解码单元，其具有多个处理部件，每个处理部件具有布置成对应于格状图的各个节点的多个单元，用于使用 具有循环型连接结构的模拟信号处理单元，其中最后一个处理部分连接到第一处理部分; 控制单元，用于并行地执行关于解码单元的处理部分的顺序指定; 模拟数据存储单元，包括与设置在解码单元中的处理部并联连接的多个电容器; 以及第一开关单元，用于在控制单元的控制下将模拟输入数据存储在模拟数据存储单元的特定电容器中。 因此，可以显着提高解码速度。

公开(公告)号：US07567197B2

公开(公告)日：2009-07-28

申请号：US12104878

申请日：2008-04-17

申请人： Jung-ho Lee ,  Hong-rak Son ,  Jung-eun Lee

发明人： Jung-ho Lee ,  Hong-rak Son ,  Jung-eun Lee

IPC分类号： H03M1/38

CPC分类号： H03K3/356139 ,  H03K5/003 ,  H03M1/36

摘要： A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity.

摘要翻译： 提供了级联比较器及其控制方法。 当多个比较器级联在一起时，通过将多相位时钟信号施加到多个比较器，使得每个比较器在先前的比较器复位之前被再生，不需要在比较器之间提供保持开关。 因此，可以减小电路的尺寸和寄生分量，高速运行电路，消除由任何保持开关引起的毛刺，从而提高系统线性度。

公开(公告)号：US20070047677A1

公开(公告)日：2007-03-01

申请号：US11487469

申请日：2006-07-17

申请人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

发明人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

IPC分类号： H03D1/00

CPC分类号： H03M13/413 ,  H03M13/6597

摘要： A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

摘要翻译： 圆形维特比解码器能够提高数据解码速度，而不受采样和保持电路的采样速度的限制。 模拟维特比解码器包括：时钟分频器，其通过除外部输入的时钟信号的时钟频率产生多个时钟信号;多个采样和保持单元，其根据从...生成的时钟信号采样和保持输入模拟数据; 时钟分频器和多路复用器，其顺序并交替地输出由采样和保持单元采样和保持的模拟数据。