公开(公告)号：US20110115761A1

公开(公告)日：2011-05-19

申请号：US13010624

申请日：2011-01-20

申请人： Manabu TAKEI ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

发明人： Manabu TAKEI ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

IPC分类号： G06F3/038 ,  G09G3/30

CPC分类号： G09G3/325 ,  G09G3/3266 ,  G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0216 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027

摘要： A display device includes a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit which applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit which generates gradation current based on a display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit which applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit which controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.

摘要翻译： 显示装置包括具有多个信号线的显示面板和具有包含电流控制型发光装置的多个显示像素的扫描线; 扫描驱动器电路，其将扫描信号施加到每条扫描线，并将连接到扫描线的显示像素设置在选择状态; 信号驱动器电路，其基于显示数据亮度灰度分量生成灰度电流，并提供给以选择状态设置的显示像素; 预充电电路，对每个信号线施加预充电电压，并且以预定的充电状态设置附接到每条扫描线的电容分量; 以及操作控制电路，当电容分量被设定在预定的充电状态时，控制发光器件在非发光状态下的设置。

公开(公告)号：US20100245343A1

公开(公告)日：2010-09-30

申请号：US12749975

申请日：2010-03-30

申请人： Manabu TAKEI ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

发明人： Manabu TAKEI ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

IPC分类号： G06F3/038

CPC分类号： G09G3/3275 ,  G09G3/3241 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/027 ,  G09G2320/043

摘要： A pixel includes a light emitting element and a driving element connected to the light emitting element. After an initial voltage is applied to one end of a current path of the driving element via the signal line, the pixel driving device acquires the threshold voltage of the driving element based on a voltage value at a terminal of the signal line when the initial voltage is cut off and the relaxation time is elapsed. The voltage-current characteristics of the driving element is acquired based on the voltage value at the terminal of the signal line when the current flows into the current path of the driving element via the signal line. The current gain value of the driving element is acquired based on the threshold voltage of the driving element. The image data is corrected based on the acquired threshold voltage.

摘要翻译： 像素包括发光元件和连接到发光元件的驱动元件。 在通过信号线将初始电压施加到驱动元件的电流路径的一端之后，像素驱动装置基于信号线的端子处的电压值来获取驱动元件的阈值电压，当初始电压 被切断，放松时间过去。 当电流经由信号线流入驱动元件的电流路径时，基于信号线的端子处的电压值来获取驱动元件的电压 - 电流特性。 基于驱动元件的阈值电压获取驱动元件的当前增益值。 基于获取的阈值电压校正图像数据。

公开(公告)号：US20100134468A1

公开(公告)日：2010-06-03

申请号：US12626731

申请日：2009-11-27

申请人： Jun OGURA ,  Manabu TAKEI ,  Shunji KASHIYAMA

发明人： Jun OGURA ,  Manabu TAKEI ,  Shunji KASHIYAMA

IPC分类号： G09G5/00

CPC分类号： G09G3/3291 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2320/043

摘要： A pixel driving device in which, after a reference voltage exceeds a threshold voltage of a drive transistor is impressed through the signal lines on each pixel equipping a light emitting element and the drive transistor, set the signal lines in a state of high impedance, and acquires a voltage value of one end of the signal lines subsequent to a predetermined settling time elapsing, and acquires the threshold voltage of the drive transistor for each pixel and the current amplification factor of the pixel drive circuit as a first property parameter based on acquired voltage values at the time a plurality of first settling times longer than a predetermined value and acquires an irregularity parameter indicating the irregularity in the current amplification factor based on the value of the first property parameter and the measured voltage value acquired at the time shorter than the predetermined value.

摘要翻译： 一种像素驱动装置，其中，在参考电压超过驱动晶体管的阈值电压的情况下，通过装配发光元件和驱动晶体管的每个像素上的信号线施加脉冲，将信号线设置为高阻抗状态，以及 获取在经过预定的建立时间之后的信号线的一端的电压值，并且基于获取的电压获取每个像素的驱动晶体管的阈值电压和像素驱动电路的当前放大系数作为第一属性参数 在多个第一建立时间比预定值多的时间值，并且基于第一属性参数的值和在比预定时间短的时间获取的测量电压值来获取指示当前放大因子的不规则性的不规则参数 值。

公开(公告)号：US20090206398A1

公开(公告)日：2009-08-20

申请号：US12427322

申请日：2009-04-21

申请人： Koh YOSHIKAWA ,  Akio SUGI ,  Kouta TAKAHASHI ,  Manabu TAKEI ,  Haruo NAKAZAWA ,  Noriyuki IWAMURO

发明人： Koh YOSHIKAWA ,  Akio SUGI ,  Kouta TAKAHASHI ,  Manabu TAKEI ,  Haruo NAKAZAWA ,  Noriyuki IWAMURO

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US20070292995A1

公开(公告)日：2007-12-20

申请号：US11843152

申请日：2007-08-22

申请人： Michio NEMOTO ,  Manabu TAKEI ,  Tatsuya NAITO

发明人： Michio NEMOTO ,  Manabu TAKEI ,  Tatsuya NAITO

IPC分类号： H01L21/332

CPC分类号： H01L29/0646 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/7395

摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

摘要翻译： 没有显示隔离区域对反向恢复峰值电流的不利影响的反向阻挡半导体器件，其具有显示令人满意的软恢复的击穿耐受结构，其抑制基本上伴随常规反向阻断IGBT的反向漏电流的恶化，并且 公开了令人满意的低导通电压。 该器件包括形成在n漂移层上的MOS栅极结构，该MOS栅极结构包括形成在该漂移层的前表面区域中的p +基极层，形成在该基极层的表面区域中的n +发射极区域， 覆盖发射极区域和漂移层之间的基底层的表面区域的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。 发射极电极与MOS栅极结构的发射极区域和基极层接触。 p +隔离区域通过漂移层包围MOS栅极结构，并延伸穿过漂移层的整个厚度。 p +集电极层形成在漂移层的后表面上并连接到隔离区的后侧。 距离W大于厚度d，其中距离W是距离发射电极的一部分的最外侧位置（与基层接触的部分）到隔离区域的最内位置的距离，以及 厚度d是漂移层的深度方向的尺寸。

公开(公告)号：US20080153212A1

公开(公告)日：2008-06-26

申请号：US12025422

申请日：2008-02-04

申请人： Manabu TAKEI

发明人： Manabu TAKEI

IPC分类号： H01L21/331

CPC分类号： H01L29/42356 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n−-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

摘要翻译： 半导体器件及其制造方法包括其上选择性地形成氧化物膜的单晶硅衬底。 在氧化膜上形成栅极多晶硅。 栅极多晶硅的表面被栅极氧化膜覆盖，该栅极氧化物膜的表面被杂质浓度高于衬底的n型掺杂的阴极膜覆盖，作为n型 层。 在阴极膜中，与衬底接触的部分成为具有高杂质浓度的n + +缓冲区，接着形成p基区。 在p基区旁边，形成n + SUP源源区。 在阴极膜上，选择性地形成层间绝缘膜，在其上形成发射电极。 以高速率的可接受的产品获得诸如IGBT的半导体器件，具有优异的导通电压到关断损耗折衷和优良的导通电压对击穿电压的折衷。

公开(公告)号：US20100264455A1

公开(公告)日：2010-10-21

申请号：US12824541

申请日：2010-06-28

申请人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

发明人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

IPC分类号： H01L29/739 ,  H01L29/06

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。

公开(公告)号：US20090317959A1

公开(公告)日：2009-12-24

申请号：US12489884

申请日：2009-06-23

申请人： Manabu TAKEI

发明人： Manabu TAKEI

IPC分类号： H01L21/20

CPC分类号： H01L29/66712 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66136 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

摘要翻译： 用于制造超结半导体器件的制造方法在表现出低电阻的n型半导体衬底上表现出高电阻的n型外延层上形成氧化物膜和氮化物膜。 划线区域中的氮化物膜的部分通过图案化而不被去除，并且通过氮化物膜打开取向标记。 在氧化物膜中打开沟槽图案之后，形成具有高纵横比的沟槽。 去除划线区域外部的氧化膜部分，将p型外延层埋设在沟槽中。 相对于氮化物膜研磨过度生长的p型外延层，通过蚀刻完成研磨表面，露出n型外延层表面。

公开(公告)号：US20120184083A1

公开(公告)日：2012-07-19

申请号：US13352581

申请日：2012-01-18

申请人： Kazuo SHIMOYAMA ,  Manabu TAKEI ,  Haruo NAKAZAWA

发明人： Kazuo SHIMOYAMA ,  Manabu TAKEI ,  Haruo NAKAZAWA

IPC分类号： H01L21/78

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

摘要翻译： 在其上形成有形成半导体芯片的顶表面结构和底表面结构的薄半导体晶片被固定到支撑衬底。 然后，在晶片上形成成为划线的沟槽，其上露出一个晶面以形成沟槽的侧壁。 在该侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与作为底表面扩散层的ap集电极区域接触的同时延伸到顶表面侧 。 然后，进行激光切割以与p收集区一起形成在集电极区上形成的集电极。

公开(公告)号：US20100093164A1

公开(公告)日：2010-04-15

申请号：US12575730

申请日：2009-10-08

申请人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

发明人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

IPC分类号： H01L21/22

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。