公开(公告)号：US5374571A

公开(公告)日：1994-12-20

申请号：US72802

申请日：1993-06-07

申请人： Satyendranath Mukherjee ,  Manjin J. Kim

发明人： Satyendranath Mukherjee ,  Manjin J. Kim

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using edges of the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

摘要翻译： 提供了一种具有改善的耐用性的半导体器件，其包括在其主表面上具有第一导电类型的区域的半导体衬底; 在所述第一导电类型的区域内选择性地形成相反导电类型的第一基区; 选择性地形成在所述第一基极区内并具有比所述第一基极区更高的杂质浓度的相反导电类型的第二基极区; 在所述第一和第二基极区域内形成并覆盖所述第二基极区域的一种导电类型的源极区域; 以及与沟槽区域相对的多晶硅栅电极，栅极绝缘层插入其间; 其中所述第二基极区域和所述源极区域基本上完全形成在所述第一基极区域内; 所述第二基极区域的深度小于所述第一基极区域，并且形成在足够接近所述沟道区域的距离处，以有效地减小所述第一基极区域中的寄生电阻，所述第二基极区域的侧向边缘基本上与所述侧向 栅电极的边缘; 通过使用多晶硅栅极的边缘作为自对准掩模通过多晶硅栅电极区域的顺序注入形成第一基极区域和源极区域，然后使用多晶硅栅极电极注入第二基极区域而没有实质的横向扩散 作为面具; 并且所述多晶硅栅电极具有足以掩盖所述第一基极区域中所选择的深度植入的厚度。

公开(公告)号：US5268586A

公开(公告)日：1993-12-07

申请号：US842853

申请日：1992-02-25

申请人： Satyendranath Mukherjee ,  Manjin J. Kim

发明人： Satyendranath Mukherjee ,  Manjin J. Kim

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

摘要翻译： 提供了一种具有改善的耐用性的半导体器件，其包括在其主表面上具有第一导电类型的区域的半导体衬底; 在所述第一导电类型的区域内选择性地形成相反导电类型的第一基区; 选择性地形成在所述第一基极区内并具有比所述第一基极区更高的杂质浓度的相反导电类型的第二基极区; 在所述第一和第二基极区域内形成并覆盖所述第二基极区域的一种导电类型的源极区域; 以及与沟槽区域相对的多晶硅栅电极，栅极绝缘层插入其间; 其中所述第二基极区域和所述源极区域基本上完全形成在所述第一基极区域内; 所述第二基极区域的深度小于所述第一基极区域，并且形成在足够接近所述沟道区域的距离处，以有效地减小所述第一基极区域中的寄生电阻，所述第二基极区域的侧向边缘基本上与所述侧向 栅电极的边缘; 通过使用多晶硅栅电极作为自对准掩模通过多晶硅栅极电极区域的顺序注入形成第一基极区域和源极区域，然后使用多晶硅栅极电极注入第二基极区域，而不会实质上横向扩散 面具; 并且所述多晶硅栅电极具有足以掩盖所述第一基极区域中所选择的深度植入的厚度。

公开(公告)号：US5486485A

公开(公告)日：1996-01-23

申请号：US198243

申请日：1994-02-18

申请人： Manjin J. Kim ,  Satyendranath Mukherjee

发明人： Manjin J. Kim ,  Satyendranath Mukherjee

IPC分类号： G02F1/1335 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： G02F1/136277

摘要： A method is set forth for forming a plurality of SOI transistors in a pattern beneath planarized reflective surfaces of a reflective display. This enables the formation of information pixels useful in devices, such as reflective LCD devices. A specific technique of providing the SOI transistors is set forth.

摘要翻译： 提出了一种用于在反射显示器的平坦化反射表面下方的图案中形成多个SOI晶体管的方法。 这使得能够形成在诸如反射型LCD装置的设备中有用的信息像素。 阐述了提供SOI晶体管的具体技术。

公开(公告)号：US6011278A

公开(公告)日：2000-01-04

申请号：US959346

申请日：1997-10-28

申请人： Dev Alok ,  Satyendranath Mukherjee ,  Emil Arnold

发明人： Dev Alok ,  Satyendranath Mukherjee ,  Emil Arnold

IPC分类号： H01L29/16 ,  H01L21/337 ,  H01L21/338 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812 ,  H01L29/861 ,  H01L31/0256 ,  H01L23/58 ,  H01L31/0312

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/7835 ,  H01L29/8611 ,  H01L2924/0002

摘要： A lateral silicon carbide (SiC) semiconductor device includes a SIC substrate of a first conductivity type, a SiC epitaxial layer of the first conductivity type on the substrate and a SiC surface layer on the SiC epitaxial layer. The SiC surface layer has a SiC first region of the first conductivity type, a SiC lateral drift region of a second conductivity type opposite to that of the first conductivity type adjacent the first region and forming a p-n junction therewith, and a SiC second region of the second conductivity type spaced apart from the first region by the drift region. By providing the drift region with a variable doping level which increases in a direction from the first region to the second region, compact SiC semiconductor devices such as high-voltage diodes or MOSFETs can be formed which can operate at high voltages, high temperatures and high frequencies, thus providing a substantial advantage over known devices.

摘要翻译： 横向碳化硅（SiC）半导体器件包括第一导电类型的SIC衬底，衬底上的第一导电类型的SiC外延层和SiC外延层上的SiC表面层。 SiC表面层具有第一导电类型的SiC第一区域，与第一区域相邻的第二导电类型的第二导电类型的SiC侧向漂移区域并与其形成pn结，以及SiC第二区域 所述第二导电类型与所述第一区域间隔开所述漂移区域。 通过提供具有从第一区域到第二区域的方向增加的可变掺杂水平的漂移区域，可以形成可在高电压，高温和高温下工作的紧凑的SiC半导体器件，例如高压二极管或MOSFET 频率，因此比已知装置提供了显着的优点。

公开(公告)号：US5446300A

公开(公告)日：1995-08-29

申请号：US971382

申请日：1992-11-04

申请人： Michael Amato ,  Satyendranath Mukherjee ,  Paul R. Veldman ,  Armin F. Wegener

发明人： Michael Amato ,  Satyendranath Mukherjee ,  Paul R. Veldman ,  Armin F. Wegener

IPC分类号： H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/0629 ,  H01L27/0922

摘要： A semiconductor device is provided having a substrate which includes a floating circuit well with turn on/turn off signals generated by a voltage drop proximate to at least one resistor contained therein, and having high-voltage interconnects to connect the drain terminals of a plurality of LDMOS transistors to the resistor in the floating well and wherein the transistors, resistor and floating well are combined into an integrated structure which eliminates the high voltage interconnect crossovers.

摘要翻译： 提供了一种半导体器件，其具有包括浮置电路阱的衬底，其具有由接近其中包含的至少一个电阻器的电压降产生的导通/截止信号，并且具有高压互连以将多个 将LDMOS晶体管连接到浮动阱中的电阻器，并且其中晶体管，电阻器和浮动阱被组合成消除高电压互连跨接的集成结构。

公开(公告)号：US06559068B2

公开(公告)日：2003-05-06

申请号：US09894089

申请日：2001-06-28

申请人： Dev Alok ,  Emil Arnold ,  Richard Egloff ,  Satyendranath Mukherjee

发明人： Dev Alok ,  Emil Arnold ,  Richard Egloff ,  Satyendranath Mukherjee

IPC分类号： H01L21469

CPC分类号： H01L21/049

摘要： A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

摘要翻译： 提供了一种用于提高碳化硅金属氧化物半导体场效应晶体管（MOSFET）中的反型层迁移率的方法。 具体地，本发明提供了一种将氧化物层施加到碳化硅衬底上，使得所得SiC MOSFET的氧化物 - 衬底界面得到改善的方法。 该方法包括在金属杂质存在下形成氧化物层。

公开(公告)号：US5229312A

公开(公告)日：1993-07-20

申请号：US867595

申请日：1992-04-13

申请人： Satyendranath Mukherjee ,  Manjin Kim

发明人： Satyendranath Mukherjee ,  Manjin Kim

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： A nonvolatile trench memory device such as an EEPROM is made by a method which permits an extremely compact and simple configuration due to the use of precise and efficient self-alignment techniques. Oxide-capped polysilicon mesas, formed integrally with the control gates, form the word lines of the memory device, while drain metallization lines contact drain regions of the device and extend over the oxide-capped word lines to form the bit lines. The resulting device is extremely compact, since the self-aligned process permits tighter tolerances and the unique polysilicon mesa/oxide cap construction permits a more compact configuration.

公开(公告)号：US5606521A

公开(公告)日：1997-02-25

申请号：US496104

申请日：1995-06-28

申请人： Di-Son Kuo ,  Len-Yuan Tsou ,  Satyendranath Mukherjee ,  Mark Simpson

发明人： Di-Son Kuo ,  Len-Yuan Tsou ,  Satyendranath Mukherjee ,  Mark Simpson

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00 ,  G11C11/34

CPC分类号： H01L29/66825 ,  H01L29/42336

摘要： An electrically erasable and programmable read only memory (EEPROM) is provided with an insulated control gate and an insulating floating gate in a trench in a semiconductor body. A dielectric layer is disposed along the sidewalls of the trench to separate the floating gate and the semiconductor body. The thickness of the dielectric layer along at least one sidewall of the trench is greater than the thickness of the dielectric layer along the other sidewalls of the trench in order to increase the programming speed due to a higher electric field in the gate oxide along the remaining sidewalls.

摘要翻译： 电可擦除和可编程只读存储器（EEPROM）在半导体主体的沟槽中设置有绝缘控制栅极和绝缘浮置栅极。 电介质层沿沟槽的侧壁设置以分离浮栅和半导体本体。 沿着沟槽的至少一个侧壁的电介质层的厚度大于沿着沟槽的其它侧壁的电介质层的厚度，以便增加编程速度，这是由于栅极氧化物沿着剩余部分的较高电场 侧壁

公开(公告)号：US5485292A

公开(公告)日：1996-01-16

申请号：US439617

申请日：1995-05-12

申请人： Stephen Wong ,  Satyendranath Mukherjee ,  Naveed Majid

发明人： Stephen Wong ,  Satyendranath Mukherjee ,  Naveed Majid

IPC分类号： G01R15/06 ,  G01R19/00 ,  H03K5/12 ,  H03K5/153

CPC分类号： G01R15/06

摘要： A high-voltage differential sensor includes an attenuator formed of two matched monolithic capacitance divider networks. Each divider network is formed of a series connection of monolithically integrated capacitors, which together generate an attenuated differential signal from a high-voltage differential input signal. The attenuated differential signal from the capacitance divider networks is then amplified and fed to a comparator, which generates a first output level when the high-voltage differential input signal is above a selected level, and generates a second output level when the high-voltage differential input signal is below the selected level. By using monolithically integrated capacitors in the divider networks of the attenuator, a simple, compact, low power, high performance high-voltage differential sensor is obtained.

摘要翻译： 高压差分传感器包括由两个匹配的单片电容分压器网络形成的衰减器。 每个分压网络由单片集成电容器的串联连接形成，它们一起从高电压差分输入信号产生衰减的差分信号。 来自电容分压器网络的衰减的差分信号然后被放大并馈送到比较器，当比较器高电压差分输入信号高于选定电平时，该比较器产生第一输出电平，并且当高压差分 输入信号低于所选电平。 通过在衰减器的分压网络中使用单片集成电容器，可以获得简单，紧凑，低功耗，高性能的高压差分传感器。

公开(公告)号：US4939566A

公开(公告)日：1990-07-03

申请号：US115478

申请日：1987-10-30

申请人： Barry M. Singer ,  Gert W. Bruning ,  Satyendranath Mukherjee

发明人： Barry M. Singer ,  Gert W. Bruning ,  Satyendranath Mukherjee

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/739 ,  H02M3/158 ,  H03K17/00 ,  H03K17/082 ,  H03K17/567

CPC分类号： H03K17/0822 ,  H01L27/088 ,  H01L29/7393 ,  H02M3/1584 ,  H03K17/567 ,  H03K2217/0036

摘要： A semiconductor switch comprising a lateral DMOS and a lateral IGT both of which can be fabricated in a monolithic integrated circuit. In operation the lateral DMOS stays on while the lateral IGT is switched off in order to reduce turn off power dissipation.