公开(公告)号：US5268586A

公开(公告)日：1993-12-07

申请号：US842853

申请日：1992-02-25

申请人： Satyendranath Mukherjee ,  Manjin J. Kim

发明人： Satyendranath Mukherjee ,  Manjin J. Kim

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

摘要翻译： 提供了一种具有改善的耐用性的半导体器件，其包括在其主表面上具有第一导电类型的区域的半导体衬底; 在所述第一导电类型的区域内选择性地形成相反导电类型的第一基区; 选择性地形成在所述第一基极区内并具有比所述第一基极区更高的杂质浓度的相反导电类型的第二基极区; 在所述第一和第二基极区域内形成并覆盖所述第二基极区域的一种导电类型的源极区域; 以及与沟槽区域相对的多晶硅栅电极，栅极绝缘层插入其间; 其中所述第二基极区域和所述源极区域基本上完全形成在所述第一基极区域内; 所述第二基极区域的深度小于所述第一基极区域，并且形成在足够接近所述沟道区域的距离处，以有效地减小所述第一基极区域中的寄生电阻，所述第二基极区域的侧向边缘基本上与所述侧向 栅电极的边缘; 通过使用多晶硅栅电极作为自对准掩模通过多晶硅栅极电极区域的顺序注入形成第一基极区域和源极区域，然后使用多晶硅栅极电极注入第二基极区域，而不会实质上横向扩散 面具; 并且所述多晶硅栅电极具有足以掩盖所述第一基极区域中所选择的深度植入的厚度。

公开(公告)号：US5374571A

公开(公告)日：1994-12-20

申请号：US72802

申请日：1993-06-07

申请人： Satyendranath Mukherjee ,  Manjin J. Kim

发明人： Satyendranath Mukherjee ,  Manjin J. Kim

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using edges of the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

摘要翻译： 提供了一种具有改善的耐用性的半导体器件，其包括在其主表面上具有第一导电类型的区域的半导体衬底; 在所述第一导电类型的区域内选择性地形成相反导电类型的第一基区; 选择性地形成在所述第一基极区内并具有比所述第一基极区更高的杂质浓度的相反导电类型的第二基极区; 在所述第一和第二基极区域内形成并覆盖所述第二基极区域的一种导电类型的源极区域; 以及与沟槽区域相对的多晶硅栅电极，栅极绝缘层插入其间; 其中所述第二基极区域和所述源极区域基本上完全形成在所述第一基极区域内; 所述第二基极区域的深度小于所述第一基极区域，并且形成在足够接近所述沟道区域的距离处，以有效地减小所述第一基极区域中的寄生电阻，所述第二基极区域的侧向边缘基本上与所述侧向 栅电极的边缘; 通过使用多晶硅栅极的边缘作为自对准掩模通过多晶硅栅电极区域的顺序注入形成第一基极区域和源极区域，然后使用多晶硅栅极电极注入第二基极区域而没有实质的横向扩散 作为面具; 并且所述多晶硅栅电极具有足以掩盖所述第一基极区域中所选择的深度植入的厚度。

公开(公告)号：US5486485A

公开(公告)日：1996-01-23

申请号：US198243

申请日：1994-02-18

申请人： Manjin J. Kim ,  Satyendranath Mukherjee

发明人： Manjin J. Kim ,  Satyendranath Mukherjee

IPC分类号： G02F1/1335 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： G02F1/136277

摘要： A method is set forth for forming a plurality of SOI transistors in a pattern beneath planarized reflective surfaces of a reflective display. This enables the formation of information pixels useful in devices, such as reflective LCD devices. A specific technique of providing the SOI transistors is set forth.

摘要翻译： 提出了一种用于在反射显示器的平坦化反射表面下方的图案中形成多个SOI晶体管的方法。 这使得能够形成在诸如反射型LCD装置的设备中有用的信息像素。 阐述了提供SOI晶体管的具体技术。

公开(公告)号：US4981816A

公开(公告)日：1991-01-01

申请号：US445130

申请日：1989-11-30

申请人： Manjin J. Kim ,  Dale M. Brown

发明人： Manjin J. Kim ,  Dale M. Brown

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76855 ,  H01L21/28512 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/02

摘要： A metal for fabricating contact structures through via openings in VLSI circuits employs a dual layer of refractory metal. A thin titanium layer is deposited, over which a molybdenum layer is formed. An annealing treatment further improves contact resistance characteristics. The method results in a contact structure which exhibits desirable properties of thermal compatibility, step coverage, contact resistance and improved processing characteristics.

摘要翻译： 用于通过VLSI电路中的通孔开口制造接触结构的金属采用双层难熔金属。 沉积薄的钛层，在其上形成钼层。 退火处理进一步提高了接触电阻特性。 该方法产生显示出所需性质的热相容性，台阶覆盖率，接触电阻和改进的加工特性的接触结构。

公开(公告)号：US5681761A

公开(公告)日：1997-10-28

申请号：US580409

申请日：1995-12-28

申请人： Manjin J. Kim

发明人： Manjin J. Kim

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265 ,  H01L27/12

CPC分类号： H01L29/66772 ,  H01L2924/0002

摘要： A technique for making a microwave, high power SOI-MOFET device is set forth together with such a device. An important aspect of this structure is the presence of high conductivity metal gate fingers for the device.

摘要翻译： 与这种装置一起提出了制造微波，高功率SOI-MOFET器件的技术。 该结构的一个重要方面是用于器件的高导电性金属栅极指状物的存在。

公开(公告)号：US4871617A

公开(公告)日：1989-10-03

申请号：US595800

申请日：1984-04-02

申请人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

发明人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/28512 ,  H01L21/76879 ,  Y10T428/12528 ,  Y10T428/12597 ,  Y10T428/12826 ,  Y10T428/1284

摘要： A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon of low resistivity to form a low resistance contact therewith.

摘要翻译： 由钛和钨的合金的第一导体和诸如钼的难熔金属的第二导体组成的导电构件被烧结到具有低电阻率的硅的导电构件以与其形成低电阻接触。

公开(公告)号：US4849377A

公开(公告)日：1989-07-18

申请号：US866648

申请日：1986-05-27

申请人： Manjin J. Kim ,  Bruce F. Griffing ,  Ronald H. Wilson ,  Arlene G. Williams ,  Robert W. Stoll

发明人： Manjin J. Kim ,  Bruce F. Griffing ,  Ronald H. Wilson ,  Arlene G. Williams ,  Robert W. Stoll

IPC分类号： H01L21/318 ,  H01L21/768

CPC分类号： H01L21/318 ,  H01L21/76879

摘要： Molybdenum gate electrode material is provided with an upper layer of molybdenum nitride which acts to prevent deposition of source and drain contact metal by selective chemical vapor deposition (CVD). The nitride layer also provides an improved mask for ion implantation process steps. This results in an FET structure exhibiting a high degree of planarity which is desirable for multilevel device fabrication.

摘要翻译： 钼栅极材料设置有上层的氮化钼，其用于通过选择性化学气相沉积（CVD）来防止源极和漏极接触金属的沉积。 氮化物层还提供用于离子注入工艺步骤的改进的掩模。 这导致具有高度平面度的FET结构，这对于多电平器件制造是期望的。

公开(公告)号：US06235601B1

公开(公告)日：2001-05-22

申请号：US08934301

申请日：1997-09-19

申请人： Manjin J. Kim

发明人： Manjin J. Kim

IPC分类号： H01L21331

CPC分类号： H01L29/66265 ,  Y10S148/01 ,  Y10S148/15

摘要： A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

摘要翻译： 阐述了提供自对准的垂直双极晶体管的过程。 提供了一种受控技术，用于提供晶体管的基极和发射极特征，其适当的尺寸和性质可用于高频微波应用。 通过这种技术提供微波晶体管。

公开(公告)号：US4429011A

公开(公告)日：1984-01-31

申请号：US362682

申请日：1982-03-29

申请人： Manjin J. Kim ,  Tat-Sing P. Chow

发明人： Manjin J. Kim ,  Tat-Sing P. Chow

IPC分类号： C23C8/24 ,  H01L21/28 ,  H01L21/318 ,  H01L21/321 ,  B05D5/12 ,  H01L21/306

CPC分类号： H01L21/28079 ,  C23C8/24 ,  H01L21/28105 ,  H01L21/318 ,  H01L21/321

摘要： A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of ammonia in the range from about 400.degree. C. to 850.degree. C. for a time to cause the atmosphere to react with the conductor to convert a portion of the conductor into molybdenum nitride.

摘要翻译： 描述了一种复合导电结构，其包括绝缘基板，其上设置有由氮化钼层覆盖的钼的导体以及制造该结构的方法。 该方法包括在约400℃至850℃的氨气氛中加热钼导体一段时间，使气氛与导体反应，将一部分导体转变为氮化钼。

公开(公告)号：US5405794A

公开(公告)日：1995-04-11

申请号：US259769

申请日：1994-06-14

申请人： Manjin J. Kim

发明人： Manjin J. Kim

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/126

摘要： A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

摘要翻译： 垂直双扩散金属对半导体器件通过一种方法产生，该方法包括通过自对准工艺和剥离工艺形成水平分离的重掺杂Si和源的体，以及形成具有负斜率的沟槽 侧墙。