公开(公告)号：US07572703B2

公开(公告)日：2009-08-11

申请号：US11558283

申请日：2006-11-09

申请人： Marco Annese ,  Pietro Montanini ,  Riccardo Depetro

发明人： Marco Annese ,  Pietro Montanini ,  Riccardo Depetro

IPC分类号： H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

摘要翻译： 一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。 该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。 形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸 相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。

公开(公告)号：US20070141787A1

公开(公告)日：2007-06-21

申请号：US11558283

申请日：2006-11-09

申请人： Marco Annese ,  Pietro Montanini ,  Riccardo Depetro

发明人： Marco Annese ,  Pietro Montanini ,  Riccardo Depetro

IPC分类号： H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

摘要翻译： 一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。 该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。 形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸 相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。

公开(公告)号：US08183098B2

公开(公告)日：2012-05-22

申请号：US12610463

申请日：2009-11-02

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20100075484A1

公开(公告)日：2010-03-25

申请号：US12610463

申请日：2009-11-02

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20070296036A1

公开(公告)日：2007-12-27

申请号：US11820393

申请日：2007-06-19

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20070141809A1

公开(公告)日：2007-06-21

申请号：US11584259

申请日：2006-10-19

申请人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

发明人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

摘要翻译： 用于制造半导体芯片中的集成器件的方法设想：形成半导体层，部分地悬置在半导体衬底之上，并通过临时锚固被约束到衬底; 将层分成彼此横向分离的多个部分; 并移除临时锚地，以释放这些部分。

公开(公告)号：US07635896B2

公开(公告)日：2009-12-22

申请号：US11820393

申请日：2007-06-19

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Mottura Marta

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Mottura Marta

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US07605015B2

公开(公告)日：2009-10-20

申请号：US11584259

申请日：2006-10-19

申请人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

发明人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

摘要翻译： 用于制造半导体芯片中的集成器件的方法设想：形成半导体层，部分地悬置在半导体衬底之上，并通过临时锚固被约束到衬底; 将层分成彼此横向分离的多个部分; 并移除临时锚地，以释放这些部分。

公开(公告)号：US08035423B2

公开(公告)日：2011-10-11

申请号：US12347517

申请日：2008-12-31

申请人： Giulio Ricotti ,  Riccardo Depetro

发明人： Giulio Ricotti ,  Riccardo Depetro

IPC分类号： H03K3/00 ,  H01L27/06

CPC分类号： G01S7/523 ,  H03K3/356113 ,  H03K17/04206 ,  H03K17/6874 ,  H03K2217/0054

摘要： A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

摘要翻译： 电路包括具有第一和第二晶体管的开关和用于驱动开关的驱动装置。 耦合在第一和第二晶体管的相应公共栅极和源极端子之间的锁存电路向共用栅极端子提供第一和第二控制信号以关断第一和第二晶体管。 锁存电路包括耦合到公共源极端子的触发器，并具有通过复位电阻耦合到公共源极端子的复位端子，通过设定电阻耦合到公共源极端子的设置端子和耦合到公共源极端子的输出端子 普通门终端。 锁存电路还包括连接到触发器的设置和复位端以及公共源极的激活电路，以在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

公开(公告)号：US6043532A

公开(公告)日：2000-03-28

申请号：US965840

申请日：1997-11-07

申请人： Riccardo Depetro ,  Michele Palmieri

发明人： Riccardo Depetro ,  Michele Palmieri

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/4238

摘要： The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

摘要翻译： DMOS晶体管包括n个漏极区域，其与漏极区域形成具有至少一个具有小曲率半径的边缘部分的接合部的p体区域，限定身体区域中的通道的n +源极区域，p +体 接触区域，栅极电极，源极和主体电极以及漏极电极。 为了防止当源极，主体和栅极短路时结在反向偏置时的“回扣”现象，p +区与每个具有小曲率半径的边缘部分相关联，并且布置成 比源区域的任何部分更靠近相关联的边缘部分。