公开(公告)号：US08035423B2

公开(公告)日：2011-10-11

申请号：US12347517

申请日：2008-12-31

申请人： Giulio Ricotti ,  Riccardo Depetro

发明人： Giulio Ricotti ,  Riccardo Depetro

IPC分类号： H03K3/00 ,  H01L27/06

CPC分类号： G01S7/523 ,  H03K3/356113 ,  H03K17/04206 ,  H03K17/6874 ,  H03K2217/0054

摘要： A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

摘要翻译： 电路包括具有第一和第二晶体管的开关和用于驱动开关的驱动装置。 耦合在第一和第二晶体管的相应公共栅极和源极端子之间的锁存电路向共用栅极端子提供第一和第二控制信号以关断第一和第二晶体管。 锁存电路包括耦合到公共源极端子的触发器，并具有通过复位电阻耦合到公共源极端子的复位端子，通过设定电阻耦合到公共源极端子的设置端子和耦合到公共源极端子的输出端子 普通门终端。 锁存电路还包括连接到触发器的设置和复位端以及公共源极的激活电路，以在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

公开(公告)号：US20100164582A1

公开(公告)日：2010-07-01

申请号：US12347517

申请日：2008-12-31

申请人： Giulio Ricotti ,  Riccardo Depetro

发明人： Giulio Ricotti ,  Riccardo Depetro

IPC分类号： H03K3/356 ,  H03K3/00 ,  B06B1/02 ,  H04R23/00

CPC分类号： G01S7/523 ,  H03K3/356113 ,  H03K17/04206 ,  H03K17/6874 ,  H03K2217/0054

摘要： A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

摘要翻译： 电路包括具有第一和第二晶体管的开关和用于驱动开关的驱动装置。 耦合在第一和第二晶体管的相应公共栅极和源极端子之间的锁存电路向共用栅极端子提供第一和第二控制信号以关断第一和第二晶体管。 锁存电路包括耦合到公共源极端子的触发器，并具有通过复位电阻耦合到公共源极端子的复位端子，通过设定电阻耦合到公共源极端子的设置端子和耦合到公共源极端子的输出端子 普通门终端。 锁存电路还包括连接到触发器的设置和复位端以及公共源极的激活电路，以在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

公开(公告)号：US20090184744A1

公开(公告)日：2009-07-23

申请号：US12347525

申请日：2008-12-31

申请人： Giulio Ricotti ,  Riccardo Depetro

发明人： Giulio Ricotti ,  Riccardo Depetro

IPC分类号： H03K3/00 ,  H03K17/56 ,  H03K17/687

CPC分类号： H03K17/04206 ,  H03K17/6874

摘要： A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors. The latch circuit comprises at least one flip-flop coupled to the common source terminal and having a reset terminal coupled to the first output terminal of the driving device and to the common source terminal by means of a reset resistance, a set terminal coupled to the second output terminal of the driving device and to the common source terminal by means of a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal in order to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

摘要翻译： 开关的驱动电路包括彼此串联连接的第一和第二晶体管以及反电容器中的相对本征二极管，并且由驱动装置驱动，所述驱动装置包括连接到开关的至少一个第一和第二输出端，以将其提供给 用于在第一工作状态下驱动开关的第一控制信号和用于在第二工作状态下驱动开关的第二控制信号。 耦合在第一和第二晶体管的相应公共栅极和源极端子之间的至少一个锁存电路分别根据工作状态向共用栅极端子分别提供第一和第二控制信号，以关断和接通第一和第二晶体管 。 锁存电路包括耦合到公共源极端子的至少一个触发器，并具有通过复位电阻耦合到驱动装置的第一输出端子的复位端子，以及耦合到 驱动装置的第二输出端子和通过设定电阻和公共源极端子耦合到公共端子的输出端子。 锁存电路还包括连接到触发器的设置和复位端子和公共源极端子的激活电路，以便在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

公开(公告)号：US07924082B2

公开(公告)日：2011-04-12

申请号：US12347525

申请日：2008-12-31

申请人： Giulio Ricotti ,  Riccardo Depetro

发明人： Giulio Ricotti ,  Riccardo Depetro

IPC分类号： H03K17/16 ,  H03K17/30

CPC分类号： H03K17/04206 ,  H03K17/6874

摘要： A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors. The latch circuit comprises at least one flip-flop coupled to the common source terminal and having a reset terminal coupled to the first output terminal of the driving device and to the common source terminal by means of a reset resistance, a set terminal coupled to the second output terminal of the driving device and to the common source terminal by means of a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal in order to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

摘要翻译： 开关的驱动电路包括彼此串联连接的第一和第二晶体管以及反电容器中的相对本征二极管，并且由驱动装置驱动，所述驱动装置包括连接到开关的至少一个第一和第二输出端，以将其提供给 用于在第一工作状态下驱动开关的第一控制信号和用于在第二工作状态下驱动开关的第二控制信号。 耦合在第一和第二晶体管的相应公共栅极和源极端子之间的至少一个锁存电路分别根据工作状态向共用栅极端子分别提供第一和第二控制信号，以关断和接通第一和第二晶体管 。 锁存电路包括耦合到公共源极端子的至少一个触发器，并具有通过复位电阻耦合到驱动装置的第一输出端子的复位端子，以及耦合到 驱动装置的第二输出端子和通过设定电阻和公共源极端子耦合到公共端子的输出端子。 锁存电路还包括连接到触发器的设置和复位端子和公共源极端子的激活电路，以便在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

公开(公告)号：US6043532A

公开(公告)日：2000-03-28

申请号：US965840

申请日：1997-11-07

申请人： Riccardo Depetro ,  Michele Palmieri

发明人： Riccardo Depetro ,  Michele Palmieri

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/4238

摘要： The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

摘要翻译： DMOS晶体管包括n个漏极区域，其与漏极区域形成具有至少一个具有小曲率半径的边缘部分的接合部的p体区域，限定身体区域中的通道的n +源极区域，p +体 接触区域，栅极电极，源极和主体电极以及漏极电极。 为了防止当源极，主体和栅极短路时结在反向偏置时的“回扣”现象，p +区与每个具有小曲率半径的边缘部分相关联，并且布置成 比源区域的任何部分更靠近相关联的边缘部分。

公开(公告)号：US5852314A

公开(公告)日：1998-12-22

申请号：US643152

申请日：1996-04-30

申请人： Riccardo Depetro ,  Claudio Contiero ,  Antonio Andreini

发明人： Riccardo Depetro ,  Claudio Contiero ,  Antonio Andreini

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58 ,  H01L29/94

CPC分类号： H01L29/0878 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/42368

摘要： N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.

摘要翻译： 集成在BiCMOS集成电路中并利用RESURF条件的用于高电压的N沟道LDMOS和p沟道MOS器件具有与外延层相同类型的导电性的掩埋区域和掺杂水平之间的掺杂水平 外延层和阱区的掺杂水平。 这些器件可能被配置为源或漏源从器件而没有问题。

公开(公告)号：US09041121B2

公开(公告)日：2015-05-26

申请号：US13615220

申请日：2012-09-13

申请人： Riccardo Depetro ,  Aldo Vittorio Novelli ,  Ignazio Salvatore Bellomo

发明人： Riccardo Depetro ,  Aldo Vittorio Novelli ,  Ignazio Salvatore Bellomo

IPC分类号： H01L27/06 ,  H01K1/18 ,  H01L29/78 ,  H01L29/861 ,  H01L49/02 ,  H01L29/06

CPC分类号： H01L29/7817 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7818 ,  H01L29/861

摘要： A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

摘要翻译： 一种包括高压晶体管的半导体结构; 降压电路，其至少一部分与高压晶体管重叠; 至少一个到所述降压电路的中间接触点，连接到所述降压电路的第一和第二端之间的至少一个中间位置; 以及将所述至少一个中间接触点连接到所述半导体结构外部的至少一个外部连接。

公开(公告)号：US20100075484A1

公开(公告)日：2010-03-25

申请号：US12610463

申请日：2009-11-02

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20070296036A1

公开(公告)日：2007-12-27

申请号：US11820393

申请日：2007-06-19

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20070141809A1

公开(公告)日：2007-06-21

申请号：US11584259

申请日：2006-10-19

申请人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

发明人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

摘要翻译： 用于制造半导体芯片中的集成器件的方法设想：形成半导体层，部分地悬置在半导体衬底之上，并通过临时锚固被约束到衬底; 将层分成彼此横向分离的多个部分; 并移除临时锚地，以释放这些部分。