-
1.发明授权Monolithically integratable telephone circuit for generating control signals for displaying telephone charges 失效用于产生显示电话费用的控制信号的单片可积分电话电路
公开(公告)号：US4638122A
公开(公告)日：1987-01-20
申请号：US731167
申请日：1985-05-06
CPC分类号： H04M15/00
摘要： A telephone circuit which may be monolithically integrated, for generating control signals for displaying the telephone charges to a telephone user, is coupled to a AC voltage signal generator having a predetermined amplitude and frequency which are constant over time. The circuit includes a voltage generator for generating voltage signals which are spaced over time and have a trapezoidal pulse waveshape. A multiplier circuit calculates the product of the signals supplied by the two generators and supplies a signal which is sent to the speech circuit of the subscriber's line and is added to the speech (i.e.--conversation) signals. The circuit also includes a circuit for receiving an image signal of the overall signal adapted to the telephone line; a high-pass filter for eliminating the speech signal components from the image signal; a rectifier circuit for rectifying the filtered signal and a comparator for comparing the rectified signal with a reference signal. If the amplitude of the rectified signal is greater than the amplitude of the reference signal, the comparator generates a signal designed to stop the increase in the level of the trapezoidal pulse signals generated by the voltage generator thereby regulating the amplitude of the trapezoidal pulse signals.
摘要翻译： 可以单片集成的用于产生用于向电话用户显示电话费用的控制信号的电话电路被耦合到具有一定时间长度的预定幅度和频率的AC电压信号发生器。 该电路包括用于产生电压信号的电压发生器，其随时间间隔并具有梯形脉冲波形。 乘法器电路计算由两个发生器提供的信号的乘积，并提供发送到用户线路的语音电路并被添加到语音（即会话）信号的信号。 电路还包括用于接收适合于电话线的整体信号的图像信号的电路; 用于从图像信号中消除语音信号分量的高通滤波器; 用于整流滤波信号的整流电路和用于将整流信号与参考信号进行比较的比较器。 如果整流信号的幅度大于参考信号的振幅，则比较器产生一个信号，该信号被设计成停止由电压发生器产生的梯形脉冲信号的电平的增加，从而调节梯形脉冲信号的幅度。
-
公开(公告)号：US5877645A
公开(公告)日：1999-03-02
申请号：US908573
申请日：1997-08-08
摘要： A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.
摘要翻译： 用于补偿对数放大器的输入失调电压的电路包括数字比较器，逻辑电路和反馈回路中的数模转换器（DAC）。 比较器连接到对数放大器的输出，当放大器输入设置为零时，数字地表示输入失调电压的极性。 逻辑电路使用比较器的数字输出形成可调数字补偿信号。 该数字补偿信号被施加到DAC以产生模拟补偿信号，该信号被注入到对数放大器的输入端以消除输入失调电压。 重复该过程，直到产生适当或最佳的补偿信号。
-
3.发明授权Sampling receiver with multi-branch sigma-delta modulators and digital channel mismatch correction 失效具有多分支Σ-Δ调制器的采样接收机和数字信道不匹配校正
公开(公告)号：US6075820A
公开(公告)日：2000-06-13
申请号：US864046
申请日：1997-05-28
申请人： Vittorio Comino , Allen Chung-Li Lu
发明人： Vittorio Comino , Allen Chung-Li Lu
摘要： An IF sampling receiver for use in a wireless communication system includes first and second channels, with one channel generating an in-phase (I) component of an incoming analog IF signal, and the other channel generating a quadrature (Q) component of the analog IF signal. Each of the two channels of the IF sampling receiver includes a corresponding sigma-delta modulator channel. Each of the two sigma-delta modulator channels may be separated into m parallel branches by applying a polyphase decomposition technique to one or more resonators associated with the sigma-delta modulator. The invention thus provides a general framework for configuring a given channel of a sigma-delta modulator to include m parallel branches. The invention also provides a technique for separating a given sigma-delta modulator into n parallel channels, where n is greater than 2. Each of the n parallel channels may then be separated into m parallel branches. Mismatch between the first and second channels of the IF sampling receiver may be corrected by using a ratio of first and second channel power levels, as measured during a calibration mode, to multiply one of the I or Q components during normal operation, such that the I and Q components are brought back into balance to a first order approximation.
摘要翻译： 用于无线通信系统的IF采样接收机包括第一和第二信道，其中一个信道产生输入模拟IF信号的同相（I）分量，而另一个信道产生模拟信号的正交（Q）分量 IF信号。 IF采样接收机的两个通道中的每一个包括相应的Σ-Δ调制器通道。 通过将多相分解技术应用于与Σ-Δ调制器相关联的一个或多个谐振器，两个Σ-Δ调制器通道中的每一个可以分离成m个并行分支。 因此，本发明提供了用于配置Σ-Δ调制器的给定信道以包括m个并行分支的一般框架。 本发明还提供了一种用于将给定的Σ-Δ调制器分离成n个并行信道的技术，其中n大于2.然后可以将n个并行信道中的每一个分离成m个并行分支。 IF采样接收机的第一和第二信道之间的不匹配可以通过使用在校准模式期间测量的第一和第二信道功率电平的比率来在正常操作期间乘以I或Q分量之一来校正，使得 将I和Q分量恢复到一阶近似的平衡。
-
公开(公告)号：US5748681A
公开(公告)日：1998-05-05
申请号：US549363
申请日：1995-10-27
申请人： Vittorio Comino , Gerard Joseph Foschini , Isam M. Habbab , Sanjay Kasturia , Jack Salz , Michael Edward Prise , Ravi Subramanian
发明人： Vittorio Comino , Gerard Joseph Foschini , Isam M. Habbab , Sanjay Kasturia , Jack Salz , Michael Edward Prise , Ravi Subramanian
CPC分类号： H04L25/061 , H04L7/046 , H04L7/027 , H04L7/041 , H04L7/10
摘要： DC offset cancellation and timing recovery is provided in a homodyne receiver. The homodyne receiver demodulates an RF signal to produce a baseband signal. An initial offset correction module determines an initial DC offset of the baseband signal. An initial offset correction is applied to the baseband signal to provide an initial corrected baseband signal. Wherein, a dynamic DC offset correction module determines a dynamic DC offset. A dynamic DC offset correction is applied to the initial corrected baseband signal providing a dynamic corrected baseband signal. A timing signal is acquired from the baseband signal for synchronizing the receiver to a transmitter. A method for correcting DC offset of a baseband signal in a homodyne receiver is also described.
摘要翻译： 在零差接收机中提供DC偏移消除和定时恢复。 零差接收机解调RF信号以产生基带信号。 初始偏移校正模块确定基带信号的初始DC偏移。 对基带信号施加初始偏移校正以提供初始校正的基带信号。 其中，动态DC偏移校正模块确定动态DC偏移。 将动态DC偏移校正应用于提供动态校正基带信号的初始校正基带信号。 从用于使接收机同步到发射机的基带信号获取定时信号。 还描述了用于校正零差接收机中的基带信号的DC偏移的方法。
-
公开(公告)号：US5914633A
公开(公告)日：1999-06-22
申请号：US906912
申请日：1997-08-08
CPC分类号： H03H11/1291 , H03H2210/021 , H03H2210/043
摘要： A tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter. A decoder converts the RC product as measured by the A/D converter into a digital code which, when applied to the appropriate capacitor array, sets the array capacitance to compensate for the difference between the measured RC product and the nominal design value.
摘要翻译： 用于产生用于校准用于有源RC滤波器的类型的电容器阵列的数字代码的调谐电路由具有固定参考电压作为输入的单斜率A / D转换器和依赖于 转换器内的电阻和电容的RC产品。 解码器将由A / D转换器测量的RC乘积转换为数字代码，当应用于适当的电容器阵列时，设置阵列电容以补偿所测量的RC乘积与标称设计值之间的差。
-
公开(公告)号：US5805011A
公开(公告)日：1998-09-08
申请号：US775989
申请日：1997-01-03
申请人： Vittorio Comino
发明人： Vittorio Comino
IPC分类号： H03G11/00 , G06G7/24 , H03F1/30 , H03F3/45 , H03F3/60 , H03F3/68 , H03G7/00 , H03G11/08 , G06G7/12
摘要： Temperature and technology-independent self-calibrating monolithic logarithmic amplifier systems that use integrated cascades of current-summing or voltage-summing differential-limiter gain stages are disclosed. Each stage is trimmed and stabilized by a respective bias replicator cell and a current mirror cell. The bias replicator provides a bias current control signal in response to a change in a given difference between bias currents in a differential pair of amplifiers controlled by a predetermined differential calibration voltage. The differential pair is identical to a differential pair in the limiter amplifier. The differential calibration voltage E.sub.lin is well-within the linear portion of the amplifier's transfer curve during operation, so that the proportional relation between E.sub.k and E.sub.lin, which is the same as that between the given difference between currents and the correct bias current value I.sub.B, remains constant throughout. The bias replicator signal then varies the input bias current of the limiter amplifier to correct for temperature-related and technology-related bias-current errors. The current mirror uses an op amp connected to a calibration voltage equal to the correct limit voltage of the amplifier to detect a change from that voltage across a variable calibration resistance. The current mirror provides a signal to that variable calibration resistance to cancel that change, and to matching variable load resistances in the gain cell to correct for temperature-related and technology-related load-resistance errors.
摘要翻译： 公开了使用集成级联的电流求和或电压求和差分限幅增益级的温度和技术无关的自校准单片对数放大器系统。 每个阶段由相应的偏置复制器单元和电流镜单元进行修整和稳定。 偏置复制器响应于由预定差分校准电压控制的差分对放大器中的偏置电流之间的给定差异的变化，提供偏置电流控制信号。 差分对与限幅放大器中的差分对相同。 差分校准电压Elin在运行期间良好地位于放大器传输曲线的线性部分之内，使得Ek和Elin之间的比例关系与给定的电流差和正确的偏置电流值IB之间的比例关系相同， 保持不变。 然后，偏置复制器信号改变限幅放大器的输入偏置电流，以校正温度相关和技术相关的偏置电流误差。 电流镜使用连接到等于放大器正确极限电压的校准电压的运算放大器来检测可变校准电阻上的电压的变化。 电流镜为该可变校准电阻提供信号以消除该变化，并且在增益单元中匹配可变负载电阻以校正与温度有关的技术相关的负载电阻误差。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.021 秒)