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公开(公告)号：US20080005525A1
公开(公告)日：2008-01-03
申请号：US11478106
申请日：2006-06-29
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： A method according to one embodiment may include partitioning a memory into a first partition and a second partition; storing instructions in the first partition; providing access, by at least one thread among a plurality of threads, to instructions in the first partition; dividing the second partition into a plurality of segments; storing instructions in each respective segment corresponding to each respective thread; and providing access to each respective segment for each respective thread. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译： 根据一个实施例的方法可以包括将存储器划分成第一分区和第二分区; 将指令存储在第一分区中; 通过多个线程中的至少一个线程向第一分区中的指令提供访问; 将所述第二分区划分成多个分段; 在每个相应的段中存储对应于每个相应线程的指令; 并且为每个相应的线程提供对各个段的访问。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。
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公开(公告)号：US07412584B2
公开(公告)日：2008-08-12
申请号：US10838078
申请日：2004-05-03
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3816 , G06F9/3842 , G06F12/04
摘要： Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.
摘要翻译： 公开了用于在存储器访问和其他应用中对准数据的系统和方法。 在一个实施例中，提供了一种系统，其包括存储器单元，移位器和可操作以将数据从存储器单元路由到移位器的控制逻辑，并向移位器发送数据要被移位的量的指示。 在一个实施例中，控制逻辑提供对推测执行的支持。 控制逻辑还可以允许大端和小端数据对准操作的复用，和/或数据对准操作与非数据对准操作的复用。 在一个实施例中，存储器单元，移位器和控制逻辑集成在处理单元内，诸如网络处理器中的微引擎。
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公开(公告)号：US20080022175A1
公开(公告)日：2008-01-24
申请号：US11478393
申请日：2006-06-29
IPC分类号： G01R31/28
CPC分类号： G06F9/3802 , G06F9/30043 , G06F9/342 , G06F9/3824 , G06F9/3851
摘要： A method according to one embodiment may include performing one or more fetch operations to retrieve one or more instructions from a program memory; scheduling a write instruction to write data from at least one data register into the program memory; and stealing one or more cycles from one or more of the fetch operations to write the data in the at least one data register into the program memory. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译： 根据一个实施例的方法可以包括执行一个或多个提取操作以从程序存储器检索一个或多个指令; 调度写指令以将数据从至少一个数据寄存器写入程序存储器; 以及从一个或多个获取操作中窃取一个或多个周期，以将所述至少一个数据寄存器中的数据写入程序存储器。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。
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公开(公告)号：US07257665B2
公开(公告)日：2007-08-14
申请号：US10674835
申请日：2003-09-29
申请人： Jose S. Niell , Mark B. Rosenbluth
发明人： Jose S. Niell , Mark B. Rosenbluth
IPC分类号： G06F13/00
CPC分类号： G06F9/383 , G06F9/30098 , G06F9/30101 , G06F9/3842 , G06F9/3863
摘要： A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.
摘要翻译： 分支感知先进先出（FIFO）存储器可以包括用于存储数据的存储器阵列; 用于寻址其中的存储器位置的推指针以写入数据; 用于寻址其中的存储器位置以便读取数据的弹出指针; 指针记忆 以及耦合到指针存储器的控制逻辑。 指针存储器保存弹出指针的先前的弹出指针值。 响应于接收到的程序分支信息，控制逻辑可以将指针存储器中的先前的弹出指针值恢复到弹出指针中。
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5.发明申请公开(公告)号：US20140240326A1
公开(公告)日：2014-08-28
申请号：US13780117
申请日：2013-02-28
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。
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公开(公告)号：US20140201471A1
公开(公告)日：2014-07-17
申请号：US13743795
申请日：2013-01-17
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
IPC分类号： G06F13/16
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。
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公开(公告)号：US20140201500A1
公开(公告)日：2014-07-17
申请号：US13743833
申请日：2013-01-17
申请人： Jose S. Niell , Ramadass Nagarajan
发明人： Jose S. Niell , Ramadass Nagarajan
IPC分类号： G06F15/78
CPC分类号： G06F15/7807 , G06F13/4059 , G06F21/70 , G06F2213/0026 , G06F2213/0038 , G06F2221/2101 , G06F2221/2141 , H04L47/622
摘要： In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，诸如芯片上的系统的处理器的结构包括至少一个数据缓冲器，其包括多个条目，每个条目用于存储要传送到多个代理和从存储器传送到和从存储器传输的数据，请求 跟踪器，以跟踪要输出到结构的有序域的待处理请求;以及输出节流逻辑，用于控制从核心代理的写入事务和从存储器读取完成事务之间对有序域的分配。 描述和要求保护其他实施例。
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公开(公告)号：US20140281197A1
公开(公告)日：2014-09-18
申请号：US13997437
申请日：2013-03-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/1027 , Y02D10/13
摘要： In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，冲突检测逻辑被配置为从芯片上的系统的相干结构（SoC）的仲裁器接收多个存储器请求。 当与第一地址相关联的指示符指示相干结构具有对第一地址的控制时，冲突检测逻辑包括窥探过滤器逻辑，以将第一地址的第一窥探存储器请求降级到未播放的存储器请求。 描述和要求保护其他实施例。
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