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公开(公告)号：US07413967B2
公开(公告)日：2008-08-19
申请号：US11468030
申请日：2006-08-29
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and define a first single-crystal Si region. Next, silicon-germanium (SiGe) mixture is deposited on top of the structure in a SiGe deposition condition so as to grow (i) a second single-crystal silicon region grows up from the top surface of the first single-crystal silicon region and (ii) first and second polysilicon regions from the top surfaces of the first and second STI regions, respectively. By increasing SiGe deposition temperature and/or lowering precursor flow rate until the resulting yield is within a pre-specified range, a satisfactory SiGe deposition condition can be determined for mass production of the structure.
摘要翻译： 一种用于确定SiGe沉积条件以提高半导体结构的产量的方法。 半导体结构的制造以单晶硅（Si）层开始。 然后，在单晶Si层中形成第一和第二浅沟槽隔离（STI）区域。 STI区域夹持并限定第一单晶Si区域。 接下来，硅锗（SiGe）混合物以SiGe沉积条件沉积在结构的顶部，以便生长（i）第二单晶硅区域从第一单晶硅区域的顶表面生长， （ii）分别来自第一和第二STI区域的顶表面的第一和第二多晶硅区域。 通过提高SiGe沉积温度和/或降低前驱体流速直到得到的产率达到预定范围内，可以确定满足SiGe沉积条件以进行大规模生产。
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公开(公告)号：US07118995B2
公开(公告)日：2006-10-10
申请号：US10709644
申请日：2004-05-19
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and define a first single-crystal Si region. Next, silicon-germanium (SiGe) mixture is deposited on top of the structure in a SiGe deposition condition so as to grow (i) a second single-crystal silicon region grows up from the top surface of the first single-crystal silicon region and (ii) first and second polysilicon regions from the top surfaces of the first and second STI regions, respectively. By increasing SiGe deposition temperature and/or lowering precursor flow rate until the resulting yield is within a pre-specified range, a satisfactory SiGe deposition condition can be determined for mass production of the structure.
摘要翻译： 一种用于确定SiGe沉积条件以提高半导体结构的产量的方法。 半导体结构的制造以单晶硅（Si）层开始。 然后，在单晶Si层中形成第一和第二浅沟槽隔离（STI）区域。 STI区域夹持并限定第一单晶Si区域。 接下来，硅锗（SiGe）混合物以SiGe沉积条件沉积在结构的顶部，以便生长（i）第二单晶硅区域从第一单晶硅区域的顶表面生长， （ii）分别来自第一和第二STI区域的顶表面的第一和第二多晶硅区域。 通过提高SiGe沉积温度和/或降低前驱体流速直到得到的产率达到预定范围内，可以确定满足SiGe沉积条件以进行大规模生产。
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公开(公告)号：US06936509B2
公开(公告)日：2005-08-30
申请号：US10665713
申请日：2003-09-19
申请人： Douglas Duane Coolbaugh , Mark D. Dupuis , Matthew D. Gallagher , Peter J. Geiss , Brett A. Philips
发明人： Douglas Duane Coolbaugh , Mark D. Dupuis , Matthew D. Gallagher , Peter J. Geiss , Brett A. Philips
IPC分类号： H01L29/73 , H01L21/20 , H01L21/331 , H01L29/732 , H01L29/737 , H01L21/8249
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.
摘要翻译： 提供一种SiGe双极晶体管，其包括其中形成有集电极和副集电极区的半导体衬底，其中集电极和副集电极形成在也存在于衬底中的隔离区之间。 每个隔离区域包括使用光刻和蚀刻形成的凹陷表面和非凹陷表面。 在衬底上形成SiGe层以及每个隔离区的凹入的非凹入表面，SiGe层包括多晶Si区和SiGe基区。 在SiGe基极区上形成图案化的绝缘体层; 并且在图案化的绝缘体层上形成发射极，并通过发射器窗口与SiGe基极区域接触。
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4.发明申请BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY 有权双极晶体管结构和方法，其中包括发射极基底界面强度公开(公告)号：US20100320571A1
公开(公告)日：2010-12-23
申请号：US12488899
申请日：2009-06-22
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/0826 , H01L29/167 , H01L29/207 , H01L29/227 , H01L29/34 , H01L29/66272
摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。
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5.发明授权Bipolar transistor structure and method including emitter-base interface impurity 有权双极晶体管结构和方法包括发射极 - 基极界面杂质公开(公告)号：US08482101B2
公开(公告)日：2013-07-09
申请号：US12488899
申请日：2009-06-22
IPC分类号： H01L29/66
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/0826 , H01L29/167 , H01L29/207 , H01L29/227 , H01L29/34 , H01L29/66272
摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。
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公开(公告)号：US06674102B2
公开(公告)日：2004-01-06
申请号：US09769640
申请日：2001-01-25
申请人： Douglas Duane Coolbaugh , Mark D. Dupuis , Matthew D. Gallagher , Peter J. Geiss , Brett A. Philips
发明人： Douglas Duane Coolbaugh , Mark D. Dupuis , Matthew D. Gallagher , Peter J. Geiss , Brett A. Philips
IPC分类号： H01L29737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.
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