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    BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY
    1.
    发明申请
    BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY 有权
    双极晶体管结构和方法，其中包括发射极基底界面强度

    公开(公告)号：US20100320571A1

    公开(公告)日：2010-12-23

    申请号：US12488899

    申请日：2009-06-22

    申请人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

    发明人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

    IPC分类号： H01L29/73 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

    摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.

    摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。

    Bipolar transistor structure and method including emitter-base interface impurity
    2.
    发明授权
    Bipolar transistor structure and method including emitter-base interface impurity 有权
    双极晶体管结构和方法包括发射极 - 基极界面杂质

    公开(公告)号：US08482101B2

    公开(公告)日：2013-07-09

    申请号：US12488899

    申请日：2009-06-22

    申请人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

    发明人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

    IPC分类号： H01L29/66

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

    摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.

    摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。

    Method of fabricating lateral diodes and bipolar transistors
    3.
    发明授权
    Method of fabricating lateral diodes and bipolar transistors 有权
    制造横向二极管和双极晶体管的方法

    公开(公告)号：US06670255B2

    公开(公告)日：2003-12-30

    申请号：US09965289

    申请日：2001-09-27

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

    IPC分类号： H01L21331

    CPC分类号： H01L27/1203 ,  H01L27/0664

    摘要： Disclosed is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.

    摘要翻译： 公开了一种制造横向半导体器件的方法，包括：提供衬底，至少具有在衬底的上部中至少形成至少一个第一掺杂剂型区域和至少一个第二掺杂剂类型区域的上硅部分，至少 第一掺杂剂类型区域中的一个与第二掺杂剂类型区域中的至少一个邻接，从而形成至少一个PN结; 以及在所述上硅部分的顶表面上形成至少一个保护岛，所述保护岛延伸所述PN结的长度并与所述第一掺杂剂型区域的一部分和邻接的第二掺杂剂型区域的一部分重叠。

    Test structure and calibration method
    7.
    发明授权
    Test structure and calibration method 有权
    测试结构和校准方法

    公开(公告)号：US08829518B2

    公开(公告)日：2014-09-09

    申请号：US13231516

    申请日：2011-09-13

    申请人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    发明人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/10

    CPC分类号： B81C99/004

    摘要： A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.

    摘要翻译： 用于测量微机电系统（MEMS）腔体高度结构和校准方法的测试结构。 该方法包括在多个电极上形成牺牲腔材料并在牺牲腔材料中形成开口。 该方法还包括在开口中形成透明或基本上透明的材料以形成透明或基本上透明的窗口。 该方法还包括基于通过透明或基本上透明的窗口获得的测量值调整牺牲腔材料的厚度。

    Interconnect structures and design structures for a radiofrequency integrated circuit
    8.
    发明授权
    Interconnect structures and design structures for a radiofrequency integrated circuit 有权
    射频集成电路的互连结构和设计结构

    公开(公告)号：US08791545B2

    公开(公告)日：2014-07-29

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

    Wiring structure and method of forming the structure
    9.
    发明授权
    Wiring structure and method of forming the structure 有权
    布线结构及形成方法

    公开(公告)号：US08569888B2

    公开(公告)日：2013-10-29

    申请号：US13114079

    申请日：2011-05-24

    申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

    摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。