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    Non-volatile memory (NVM) and logic integration
    1.
    发明授权
    Non-volatile memory (NVM) and logic integration 有权
    非易失性存储器（NVM）和逻辑集成

    公开(公告)号：US08951863B2

    公开(公告)日：2015-02-10

    申请号：US13780591

    申请日：2013-02-28

    申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    IPC分类号： H01L27/115 ,  H01L21/82 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

    摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

    摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

    Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage
    2.
    发明授权
    Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage 有权
    集成形成替代栅极晶体管和具有薄膜存储的非易失性存储单元

    公开(公告)号：US08716089B1

    公开(公告)日：2014-05-06

    申请号：US13790225

    申请日：2013-03-08

    申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    IPC分类号： H01L21/8247

    CPC分类号： H01L29/42344 ,  H01L27/11573 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

    摘要： A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.

    摘要翻译： 在NVM区域和逻辑区域中形成热氧化物。 多晶硅层形成在热氧化物的上方并被图案化以分别在逻辑和NVM区域中形成伪栅极和选择栅极。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介电层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，形成开口。 在选择栅极和开口内形成第二电介质层，并且栅极层形成在第二电介质层上并且在开口内，其中开口内的栅极层形成逻辑门，栅极层被图案化以形成 NVM地区的控制门。

    Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique
    4.
    发明授权
    Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique 有权
    使用部分替代门技术集成逻辑晶体管和非易失性存储器单元的形成

    公开(公告)号：US08741719B1

    公开(公告)日：2014-06-03

    申请号：US13790014

    申请日：2013-03-08

    申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11534 ,  H01L27/11524 ,  H01L29/66545

    摘要： A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.

    摘要翻译： 在NVM区域中形成热生长含氧栅极电介质和选择栅极。 在逻辑区域中形成高k栅极电介质，势垒层和伪栅极。 阻挡层可以包括工作功能设定材料。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介质层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，导致开口。 栅极层形成在NVM区域中的电荷存储层中并且在逻辑区域的开口内，其中开口内的栅极层与势垒层一起在逻辑区域中形成逻辑门，栅极层被图案化 以在NVM区域中形成控制门。

    Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic
    6.
    发明授权
    Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic 有权
    使用热氧化物选择栅极电介质的集成技术用于选择栅极和替代栅极用于逻辑

    公开(公告)号：US08524557B1

    公开(公告)日：2013-09-03

    申请号：US13789971

    申请日：2013-03-08

    申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

    发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

    IPC分类号： H01L21/8246

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

    摘要： A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.

    摘要翻译： 形成覆盖电荷存储层的控制栅极。 在控制栅上形成热生长含氧层。 在含氧层上方形成多晶硅层并进行平坦化。 形成第一掩模层，其限定了横向邻近控制栅极的选择栅极位置，并且形成限定逻辑门位置的第二掩模层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以导致电介质中的开口。 在开口中形成高k栅介质和逻辑门。

    Method of making a logic transistor and a non-volatile memory (NVM) cell
    7.
    发明授权
    Method of making a logic transistor and a non-volatile memory (NVM) cell 有权
    制造逻辑晶体管和非易失性存储器（NVM）单元的方法

    公开(公告)号：US09111865B2

    公开(公告)日：2015-08-18

    申请号：US13661157

    申请日：2012-10-26

    申请人： Mehul D. Shroff ,  Mark D. Hall ,  Frank K. Baker, Jr.

    发明人： Mehul D. Shroff ,  Mark D. Hall ,  Frank K. Baker, Jr.

    IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L27/115

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/66545

    摘要： An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.

    摘要翻译： 直接在NVM区域的半导体层上形成含氧化物层，在NVM区域的氧化物含有层上形成第一材料的第一部分层。 第一高k电介质层直接形成在逻辑区域中的半导体层上。 第一导电层形成在逻辑区域中的第一介电层上。 第一材料的第二部分层直接形成在NVM区域中的第一部分层上并且在逻辑区域中的第一导电层上方。 在逻辑区域中形成逻辑器件。 在NVM区域中形成NVM单元，其中如果单元是浮动栅极单元或单元是分离栅极单元，则第一和第二部分层一起用于形成电荷存储层之一。

    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION
    8.
    发明申请
    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION 有权
    非易失性存储器（NVM）和逻辑集成

    公开(公告)号：US20130267072A1

    公开(公告)日：2013-10-10

    申请号：US13780591

    申请日：2013-02-28

    申请人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

    IPC分类号： H01L21/82

    CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

    摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

    摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION
    9.
    发明申请
    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION 有权
    非易失性存储器（NVM）和逻辑集成

    公开(公告)号：US20130178027A1

    公开(公告)日：2013-07-11

    申请号：US13780574

    申请日：2013-02-28

    申请人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7881

    摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.

    摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。

    Non-volatile memory (NVM) and logic integration
    10.
    发明授权
    Non-volatile memory (NVM) and logic integration 有权
    非易失性存储器（NVM）和逻辑集成

    公开(公告)号：US08669158B2

    公开(公告)日：2014-03-11

    申请号：US13780574

    申请日：2013-02-28

    申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    IPC分类号： H01L21/336 ,  H01L29/66

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7881

    摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.

    摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。