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公开(公告)号：US08647962B2
公开(公告)日：2014-02-11
申请号：US12729911
申请日：2010-03-23
申请人： Martin Liu , Richard Chu , Hung Hua Lin , Hsin-Ting Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
发明人： Martin Liu , Richard Chu , Hung Hua Lin , Hsin-Ting Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
CPC分类号： H01L25/162 , B81B2207/012 , B81C1/00269 , B81C2203/0118 , B81C2203/035 , H01L21/187 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
摘要翻译： 本公开提供了一种接合多个基板的方法。 在一个实施例中，第一衬底包括第一接合层。 第二基板包括第二接合层。 第一接合层包括硅; 第二结合层包括铝。 第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。 还提供了一种在衬底之间具有接合区域的器件。 接合区域包括在包括硅的层和包括铝的层之间的界面。
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公开(公告)号：US20110233621A1
公开(公告)日：2011-09-29
申请号：US12729911
申请日：2010-03-23
申请人： Martin Liu , Richard Chu , Hung-Hua Lin , H. T. Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
发明人： Martin Liu , Richard Chu , Hung-Hua Lin , H. T. Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
CPC分类号： H01L25/162 , B81B2207/012 , B81C1/00269 , B81C2203/0118 , B81C2203/035 , H01L21/187 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
摘要翻译： 本公开提供了一种接合多个基板的方法。 在一个实施例中，第一衬底包括第一接合层。 第二基板包括第二接合层。 第一接合层包括硅; 第二结合层包括铝。 第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。 还提供了一种在衬底之间具有接合区域的器件。 接合区域包括在包括硅的层和包括铝的层之间的界面。
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公开(公告)号：US08445380B2
公开(公告)日：2013-05-21
申请号：US13481550
申请日：2012-05-25
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/44
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个实例中，用于形成通孔结构的方法包括在半导体衬底中形成通孔，其中通孔的通孔侧壁由半导体衬底限定; 在所述通孔侧壁上形成介电层; 从所述通孔侧壁的一部分去除所述介电层; 以及形成导电层以填充所述通孔，其中所述导电层设置在所述电介质层和所述通孔侧壁的所述部分之上。 在一个实例中，电介质层是氧化物层。
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公开(公告)号：US20120080761A1
公开(公告)日：2012-04-05
申请号：US12898408
申请日：2010-10-05
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L29/84 , H01L21/768 , H01L21/50 , H01L23/48
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
摘要翻译： 半导体器件包括衬底晶片，覆盖衬底晶片的电介质层，电介质层中的图案化导体层和覆盖导体层的第一势垒层。 硅顶片结合到电介质层。 通孔通过顶部晶片和介电层的一部分形成到第一阻挡层。 侧壁电介质层沿通孔的内壁形成，与顶部晶片相邻，距离顶部晶片的上表面一定距离，形成侧壁电介质层的肩部。 在侧壁电介质层的内侧形成侧壁阻挡层，将通孔从第一阻挡层衬套到顶部晶片的上表面。 导电层填充通孔，并且在导电层，侧壁阻挡层和顶部晶片上形成顶部阻挡层。
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公开(公告)号：US20120238091A1
公开(公告)日：2012-09-20
申请号：US13481550
申请日：2012-05-25
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/768
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个实例中，用于形成通孔结构的方法包括在半导体衬底中形成通孔，其中通孔的通孔侧壁由半导体衬底限定; 在所述通孔侧壁上形成介电层; 从所述通孔侧壁的一部分去除所述介电层; 以及形成导电层以填充所述通孔，其中所述导电层设置在所述电介质层和所述通孔侧壁的所述部分之上。 在一个实例中，电介质层是氧化物层。
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公开(公告)号：US08207595B2
公开(公告)日：2012-06-26
申请号：US12898408
申请日：2010-10-05
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
摘要翻译： 半导体器件包括衬底晶片，覆盖衬底晶片的电介质层，电介质层中的图案化导体层和覆盖导体层的第一势垒层。 硅顶片结合到电介质层。 通孔通过顶部晶片和介电层的一部分形成到第一阻挡层。 侧壁电介质层沿通孔的内壁形成，与顶部晶片相邻，距离顶部晶片的上表面一定距离，形成侧壁电介质层的肩部。 在侧壁电介质层的内侧形成侧壁阻挡层，将通孔从第一阻挡层衬套到顶部晶片的上表面。 导电层填充通孔，并且在导电层，侧壁阻挡层和顶部晶片上形成顶部阻挡层。
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公开(公告)号：US08598687B2
公开(公告)日：2013-12-03
申请号：US13481574
申请日：2012-05-25
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
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公开(公告)号：US20120235300A1
公开(公告)日：2012-09-20
申请号：US13481574
申请日：2012-05-25
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L23/48
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个示例中，通孔结构包括具有由半导体衬底限定的通孔侧壁表面的通孔。 通孔侧壁表面具有第一部分和第二部分。 在通路侧壁表面的第一部分上的通路中设置导电层，并且介电层设置在通孔侧壁表面的第二部分上。 电介质层设置在通孔侧壁表面的第二部分和导电层之间。 在一个实例中，电介质层是氧化物层。
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公开(公告)号：US20120025389A1
公开(公告)日：2012-02-02
申请号：US12846504
申请日：2010-07-29
申请人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
发明人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
CPC分类号： H01L24/94 , B81B2207/015 , B81C1/00269 , B81C2203/0109 , B81C2203/0771 , H01L23/481 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
摘要翻译： 提供晶圆级封装。 该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。 所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。 其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。
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公开(公告)号：US08648468B2
公开(公告)日：2014-02-11
申请号：US12846504
申请日：2010-07-29
申请人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
发明人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
IPC分类号： H01L23/48
CPC分类号： H01L24/94 , B81B2207/015 , B81C1/00269 , B81C2203/0109 , B81C2203/0771 , H01L23/481 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
摘要翻译： 提供晶圆级封装。 该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。 所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。 其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。
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