公开(公告)号：US20090097347A1

公开(公告)日：2009-04-16

申请号：US11872573

申请日：2007-10-15

申请人： Martin Versen ,  Helmut Schneider

发明人： Martin Versen ,  Helmut Schneider

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099

摘要： A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

摘要翻译： 一种用于访问存储器单元的逻辑内容的设备，所述存储单元包括用于存储与所述逻辑内容相关的电荷的单元容量，其中所述单元容量连接在具有位线容量的位线和参考电位之间， 该装置包括：具有小于所述位线容量的参考容量的参考节点; 以及用于在存储单元的读取或写入访问的情况下分别改变位线和参考节点的电位的电路，其中，利用第一电​​流进行位线的电位变化，并且改变 参考节点的电位用第二电流进行，其中第一电流大于第二电流。

公开(公告)号：US07542362B2

公开(公告)日：2009-06-02

申请号：US11872573

申请日：2007-10-15

申请人： Martin Versen ,  Helmut Schneider

发明人： Martin Versen ,  Helmut Schneider

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099

摘要： A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

摘要翻译： 一种用于访问存储器单元的逻辑内容的设备，所述存储单元包括用于存储与所述逻辑内容相关的电荷的单元容量，其中所述单元容量连接在具有位线容量的位线和参考电位之间， 该装置包括：具有小于所述位线容量的参考容量的参考节点; 以及用于在存储单元的读取或写入访问的情况下分别改变位线和参考节点的电位的电路，其中，利用第一电​​流进行位线的电位变化，并且改变 参考节点的电位用第二电流进行，其中第一电流大于第二电流。

公开(公告)号：US20090021996A1

公开(公告)日：2009-01-22

申请号：US12174295

申请日：2008-07-16

申请人： Martin Versen ,  Helmut Schneider

发明人： Martin Versen ,  Helmut Schneider

IPC分类号： G11C7/12 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C2029/1204

摘要： A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.

摘要翻译： 存储电路包括多个位线和可经由相应位线写入的多个存储单元。 存储电路还包括位线控制电路。 位线控制电路被配置为以位线选择性方式将一弱值写入耦合到所选位线的存储单元。

公开(公告)号：US20080205173A1

公开(公告)日：2008-08-28

申请号：US12022422

申请日：2008-01-30

申请人： Joerg Kliewer ,  Klaus Nierle ,  Martin Versen

发明人： Joerg Kliewer ,  Klaus Nierle ,  Martin Versen

IPC分类号： G01R31/02 ,  G01R31/3187 ,  G11C29/00

CPC分类号： G01R31/3004

摘要： An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

摘要翻译： 一种集成电路，包括：a）至少一个集成电压发生器，用于为相关联的集成负载产生低电压; b）连接到所述电压发生器的集成电压发生器测试逻辑，所述电压发生器在作为所述集成电压发生器的操作状态的测试操作模式中，所述电压发生器测试逻辑根据外部控制信号而在有效工作状态和待机操作状态 c）用于将所述产生的负载电压切换到所述集成负载的内部负载开关，所述内部负载开关可通过内部控制信号来控制; d）其中所述测试操作模式中的所述电压发生器测试逻辑独立于相关联的内部控制切换信号切换所述集成电压发生器的操作状态，以设置施加到该负载的所述负载电压的时间电压分布。

公开(公告)号：US07308624B2

公开(公告)日：2007-12-11

申请号：US11116875

申请日：2005-04-28

申请人： Martin Versen ,  Daewon Lee

发明人： Martin Versen ,  Daewon Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/48 ,  G01R31/2889 ,  G11C5/04 ,  G11C29/1201

摘要： A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals. The module is electrically coupled to the processor. The at least one manufactured semiconductor device is mounted on the module, and the semiconductor device has a plurality of pins at least one of which is a non-functional pin. The system is configured to provide the processor access to the semiconductor device. An external device monitors voltage at the non-functional pin of the semiconductor device.

摘要翻译： 测试系统具有处理器，模块和至少一个制造的半导体器件。 处理器配置为发送和接收测试信号。 该模块电耦合到处理器。 至少一个制造的半导体器件安装在模块上，并且半导体器件具有多个引脚，其中至少一个是非功能引脚。 该系统被配置为提供处理器对半导体器件的访问。 外部设备监视半导体器件的非功能引脚的电压。

公开(公告)号：US20060023556A1

公开(公告)日：2006-02-02

申请号：US11189018

申请日：2005-07-26

申请人： Martin Versen ,  Martin Perner

发明人： Martin Versen ,  Martin Perner

IPC分类号： G11C8/00

CPC分类号： G11C7/20 ,  G11C11/401 ,  G11C29/24

摘要： An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

摘要翻译： 集成半导体存储器具有规则的行和列线，在故障的情况下可以用冗余的行和列线代替。 在利用初始化数据项初始化存储器单元之后，数据生成器电路沿着常规行或列线将识别数据项写入存储单元。 错误的常规行或列行将替换为关联的冗余行或列行。 接下来，按照声音规则行或列行将初始化数据项写入存储单元，并且将相应的标识数据项沿故障的规则行或列行写入存储单元。 故障的常规行或列行在其存储单元中具有与替换它们的冗余行或列行相同的数据值。

公开(公告)号：US07428673B2

公开(公告)日：2008-09-23

申请号：US11214482

申请日：2005-08-29

申请人： Jörg Kliewer ,  Martin Versen

发明人： Jörg Kliewer ,  Martin Versen

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025

摘要： The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

摘要翻译： 本发明涉及一种用于确定具有布置在其上的至少一个部件的电路载体的导线配置的测试方法，其中部件中的内部线以规定的顺序连接到部件连接，并且其中部件连接被连接到 电路载体。 根据该方法，使用集成在该部件中的可控测试信号发生器将各个规定的测试信号施加到部件的每条内部线路。 施加到电路载体的连接的输出信号被分接。 此后，使用用于确定部件连接和电路载体连接之间的导线配置的外部测试装置，利用施加到部件的内部线路的相应测试信号来识别各个输出信号。

公开(公告)号：US07380182B2

公开(公告)日：2008-05-27

申请号：US10933645

申请日：2004-09-03

申请人： Peter Beer ,  Achim Schramm ,  Martin Versen

发明人： Peter Beer ,  Achim Schramm ,  Martin Versen

IPC分类号： G01R31/28

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/50

摘要： Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

摘要翻译： 提供了用于检查集成电路的输出信号的装置和方法。 一个实施例提供了一种用于根据预定义的规范来检查信号是否由集成电路的写入电路输出的方法。 在这种情况下，系统固有的外部测试装置的高精度用于在模块内检查根据规格输出集成电路的数据信号和数据采样信号。

公开(公告)号：US07340313B2

公开(公告)日：2008-03-04

申请号：US11081270

申请日：2005-03-16

申请人： Manfred Moser ,  Erwin Thalmann ,  Martin Versen

发明人： Manfred Moser ,  Erwin Thalmann ,  Martin Versen

IPC分类号： G05B9/02 ,  G06G7/70 ,  G06F19/00 ,  G06F13/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00 ,  G06F9/24 ,  G06F15/177 ,  G06F11/00 ,  G06F17/50

CPC分类号： G11C29/48 ,  G11C2029/5602

摘要： The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one data connection line (104) for outputting the internal data from the electronic circuit unit (101) and for inputting external data (106) into the electronic circuit unit (101). A changeover unit (102), which is intended to change over the data connection line (104) either to the internal data line (103) or to internal signal lines (113), and a combinational logic unit (111) for combining an initialization signal (109), which is provided by the electronic circuit unit (101) to be monitored, with an external changeover signal (108), which is supplied via a changeover signal input (107) of the electronic circuit unit (101) to be monitored, are also provided. An activation signal (114), which is output by the changeover unit (102), is used to change over the data connection line to the internal signal lines (113) when the initialization signal (109) indicates an initialization mode of the electronic circuit unit (101).

摘要翻译： 本发明提供一种用于在初始化阶段期间监测电子电路单元的装置。 该装置具有至少一个内部数据线（103），用于转发电子电路单元（101）中的内部数据（105）和用于从电子电路单元（101）输出内部数据的至少一个数据连接线（104） 并将外部数据（106）输入到电子电路单元（101）中。 用于将数据连接线（104）切换到内部数据线（103）或内部信号线（113）的转换单元（102）以及用于组合初始化的组合逻辑单元（111） 由待监视的电子电路单元（101）提供的信号（109）与通过电子电路单元（101）的转换信号输入（107）提供的外部转换信号（108）成为 也被提供。 当初始化信号（109）指示电子电路的初始化模式时，由切换单元（102）输出的激活信号（114）用于将数据连接线切换到内部信号线（113） 单位（101）。

公开(公告)号：US07263019B2

公开(公告)日：2007-08-28

申请号：US11227585

申请日：2005-09-15

申请人： Klaus Nierle ,  Martin Versen

发明人： Klaus Nierle ,  Martin Versen

IPC分类号： G11C7/00

CPC分类号： G11C5/04 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611

摘要： Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.