公开(公告)号：US09935643B1

公开(公告)日：2018-04-03

申请号：US15453567

申请日：2017-03-08

Applicant: Marvell International Ltd.

Inventor： Nick C. Chang ,  Kenneth Thet Zin Oo ,  Wyant Chan ,  Pierte Roo

IPC: H03M1/00 ,  H03M1/80 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/462 ,  H03M1/00 ,  H03M1/06 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/80 ,  H03M1/804

Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.

公开(公告)号：US09031181B1

公开(公告)日：2015-05-12

申请号：US14149308

申请日：2014-01-07

Applicant: Marvell International Ltd.

Inventor： Pierte Roo

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0033 ,  H03D3/248 ,  H04L7/0337

Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.

Abstract translation: 多端口信息通信系统包括被配置为产生参考时钟信号的参考时钟信号发生器。 该系统还包括相位控制器，其被配置为通过交错每个信息通信时钟信号的相位来基于参考时钟信号产生多个信息通信时钟信号。 相位控制器包括延迟锁定环路，被配置为基于参考时钟信号产生多个延迟锁定环路信号，以及多个时间延迟元件。 每个延迟元件被配置为通过将相应的延迟加到相应的一个延迟锁定环路信号来产生相应的一个信息通信时钟信号。 该系统包括各自包括相应发射机的信息通信设备。 每个发射机被配置为响应于相应的一个信息通信时钟信号而工作。

公开(公告)号：US08880017B1

公开(公告)日：2014-11-04

申请号：US13958915

申请日：2013-08-05

Applicant: Marvell International Ltd.

Inventor： Pierte Roo ,  Sehat Sutardja

IPC: H04B1/10 ,  H04L1/00 ,  H04B3/20 ,  H04B1/38

CPC classification number: H04L1/0041 ,  H04B1/581 ,  H04B3/23 ,  H04B3/32

Abstract: A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal.

Abstract translation: 系统包括被配置为接收复合信号的收发机。 复合信号是发射信号和接收信号的组合。 复制发射机被配置为基于发射信号生成复制发射信号。 发送消除器被配置为至少部分地通过对复合信号和复制发送信号进行电阻求和来恢复接收信号。

公开(公告)号：US09323269B1

公开(公告)日：2016-04-26

申请号：US14323067

申请日：2014-07-03

Applicant: Marvell International Ltd.

Inventor： Chih-Kai Kang ,  Wyant Chan ,  Pierte Roo

IPC: G05F3/16 ,  G05F3/20 ,  H02H7/00 ,  H02H9/00 ,  G05F3/02

CPC classification number: G05F3/02 ,  G05F1/467 ,  G05F1/468 ,  H02H9/04

Abstract: A voltage regulator includes a supply filter, a bias filter, and first and second circuits. The supply filter is configured to operate from a supply voltage, and to generate a filtered supply voltage at a first node. The supply filter includes a transistor and a capacitor. First and control terminals of the transistor receive the supply voltage. A second terminal of the transistor and a first terminal of the capacitor are connected to the first node. The first circuit is configured to operate from both the supply voltage and the filtered supply voltage, and to generate a second reference voltage based on an input reference voltage. The bias filter is configured to generate a filtered second reference voltage based on the second reference voltage. The second circuit is configured to operate from the filtered supply voltage, and to generate a regulated voltage based on the filtered second reference voltage.

Abstract translation: 电压调节器包括电源滤波器，偏置滤波器以及第一和第二电路。 电源滤波器被配置为从电源电压操作，并且在第一节点处产生经滤波的电源电压。 电源滤波器包括晶体管和电容器。 晶体管的第一个和控制端接收电源电压。 晶体管的第二端子和电容器的第一端子连接到第一节点。 第一电路被配置为从电源电压和滤波的电源电压两者操作，并且基于输入参考电压产生第二参考电压。 偏置滤波器被配置为基于第二参考电压产生滤波的第二参考电压。 第二电路被配置为根据滤波的电源电压进行工作，并且基于滤波的第二参考电压产生调节电压。

公开(公告)号：US09059675B1

公开(公告)日：2015-06-16

申请号：US13857970

申请日：2013-04-05

Applicant: Marvell International Ltd.

Inventor： Tachien David Huang ,  Kenneth Thet Zin Oo ,  Pierte Roo

IPC: H03F3/191 ,  H03H7/01 ,  H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45475 ,  H03F2200/114 ,  H03F2203/45526 ,  H03H11/126 ,  H03H2011/0488

Abstract: In some implementations, a circuit includes an operational amplifier having a positive input, a negative input, and an output, the output being connected to the negative input; a first capacitor to receive the input signal; a second capacitor connected in series with the first capacitor, the second capacitor to provide a first signal to a positive input of the operational amplifier; a first resistor connected in series with the first capacitor, the first resistor to provide a second signal to the negative input of the operational amplifier; a second resistor to receive the input signal; a third resistor connected in series with the second resistor, the third resistor to provide a third signal to the positive input of the operational amplifier; and a third capacitor connected in series with the second resistor, the third capacitor to provide a fourth signal to the negative input of the operational amplifier.

Abstract translation: 在一些实现中，电路包括具有正输入，负输入和输出的运算放大器，该输出连接到负输入; 用于接收输入信号的第一电容器; 与所述第一电容器串联连接的第二电容器，所述第二电容器向所述运算放大器的正输入端提供第一信号; 与所述第一电容器串联连接的第一电阻器，所述第一电阻器向所述运算放大器的负输入端提供第二信号; 用于接收输入信号的第二电阻器; 与所述第二电阻器串联连接的第三电阻器，所述第三电阻器向所述运算放大器的正输入端提供第三信号; 以及与所述第二电阻器串联连接的第三电容器，所述第三电容器向所述运算放大器的负输入端提供第四信号。