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    Semiconductor device
    3.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20060146891A1

    公开(公告)日：2006-07-06

    申请号：US10541678

    申请日：2004-11-19

    申请人： Hisao Kunitani ,  Satoru Tanigawa ,  Hiroshi Sonobe ,  Atsuhisa Kageyama

    发明人： Hisao Kunitani ,  Satoru Tanigawa ,  Hiroshi Sonobe ,  Atsuhisa Kageyama

    IPC分类号： H04J3/06

    CPC分类号： H03L7/07 ,  H03K5/13 ,  H03K5/1565 ,  H03L7/0814 ,  H04N5/126

    摘要： In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells stepwisely to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. According to the semiconductor device of the present invention, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

    摘要翻译： 在本发明的半导体器件中，时钟不瞬时变化，但是通过逐步移动延迟单元，使其在最大N + 1 / M个时钟（N：不小于2的整数）上改变，以使之前的参考的相位状态 信号和本参考信号的相位状态彼此一致，从而精确地将时钟与参考信号同步，并且输出时钟的占空比保持恒定。 根据本发明的半导体器件，当输入参考信号与时钟不一致的信号时，可以防止时钟的占空比不连续，并且复位到该参考信号的上升沿。

    Terminal support device mounting structure
    4.
    发明授权
    Terminal support device mounting structure 有权
    端子支撑装置安装结构

    公开(公告)号：US09074619B2

    公开(公告)日：2015-07-07

    申请号：US14238172

    申请日：2012-08-10

    申请人： Akitomo Yamauchi ,  Hiroshi Sonobe

    发明人： Akitomo Yamauchi ,  Hiroshi Sonobe

    IPC分类号： F16C1/10

    CPC分类号： F16C1/101 ,  F16C1/105 ,  F16C2361/65 ,  Y10T74/20462

    摘要： A terminal support device mounting structure has a terminal support device and a bracket. The bracket has an opening, a mounting hole, a thick portion, and an engagement portion. The thick portion is located around the opening and the mounting hole. The engagement portion is provided to extend from the thick portion in an axial line direction X. The terminal support device has a socket. The socket has a mounted portion having an introduction portion and a sliding contact portion, a pair of flanges, a flexible portion having a pawl and an arm, and a rotation restriction portion. The pawl is engaged with the engagement portion during rotation. The arm supports the pawl such that the pawl can be engaged with the engagement portion. The rotation restriction portion restricts rotation of the socket after rotation causes the pawl to pass over the engagement portion.

    摘要翻译： 终端支撑装置安装结构具有端子支撑装置和支架。 托架具有开口，安装孔，厚部和接合部。 厚部位于开口和安装孔周围。 接合部设置成在轴线方向X上从厚部延伸。终端支撑装置具有插座。 插座具有安装部，其具有导入部和滑动接触部，一对凸缘，具有棘爪和臂的柔性部以及旋转限制部。 棘爪在旋转期间与接合部分接合。 臂支撑棘爪，使得棘爪能够与接合部分接合。 旋转限制部在旋转后限制插座的旋转使得爪经过接合部。

    Semiconductor inspection method
    5.
    发明授权
    Semiconductor inspection method 失效
    半导体检测方法

    公开(公告)号：US06871308B1

    公开(公告)日：2005-03-22

    申请号：US09557088

    申请日：2000-04-21

    申请人： Hiroshi Sonobe

    发明人： Hiroshi Sonobe

    IPC分类号： H01L21/3205 ,  G01R31/02 ,  G01R31/317 ,  G06F17/50 ,  H01L21/66 ,  H01L23/52 ,  G01R31/28 ,  G01R31/26

    CPC分类号： G01R31/025

    摘要： The present invention provides a semiconductor inspection method which detects a short circuit failure of adjacent lines having the possibility of a short circuit occurring, which short circuit failure cannot be detected by the conventional semiconductor inspection methods. The semiconductor inspection method comprises steps of: extracting adjacent lines having the possibility of a short circuit occurring between the lines from a layout patter of a semiconductor (step S101), obtaining input logical values such that one of the adjacent lines has a logical value “1” while the other has a logical value “0” (step S102), and monitoring outputs of a logical circuit which receives the input logical values, thereby to compare the outputs with output logical values which are expected when the input logical values are input to the logical circuit (step S103). Therefore, the short circuit failure of the adjacent lines in the logical circuit can be correctly detected in a short time.

    摘要翻译： 本发明提供一种半导体检查方法，其检测具有发生短路的可能性的相邻线路的短路故障，通过传统的半导体检查方法无法检测出短路故障。 半导体检查方法包括以下步骤：从半导体的布局图案中提取具有在线之间发生短路的可能性的相邻线（步骤S101），获得输入逻辑值，使得相邻线之一具有逻辑值“ 1“，另一个具有逻辑值”0“（步骤S102），并且监视接收输入逻辑值的逻辑电路的输出，从而将输出与输入逻辑值输入期望的输出逻辑值进行比较 到逻辑电路（步骤S103）。 因此，可以在短时间内正确检测逻辑电路中的相邻线路的短路故障。

    Synchronous clock generation apparatus and synchronous clock generation method
    6.
    发明授权
    Synchronous clock generation apparatus and synchronous clock generation method 失效
    同步时钟发生装置和同步时钟生成方法

    公开(公告)号：US07460628B2

    公开(公告)日：2008-12-02

    申请号：US11012192

    申请日：2004-12-16

    申请人： Akihiro Suzuki ,  Hiroshi Sonobe

    发明人： Akihiro Suzuki ,  Hiroshi Sonobe

    IPC分类号： H04L7/00

    CPC分类号： G06F1/0328 ,  H04N5/126

    摘要： A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

    摘要翻译： 一种同步时钟生成装置，包括：乘法器，用于将水平同步信号乘以水平同步脉冲信号以产生乘法数据;增益可变数字LPF，用于仅从所述乘法数据中提取DC分量并且能够执行增益调整;以及控制器， 基于校正数据计算增益调整数据，锁定中心频率设定数据和LPF增益调整数据。 控制器检测与锁定中心频率的偏差量和变化量，使锁定中心频率移位，并且沿着频率轴移动锁定范围，以在偏差量大时扩大视在锁定范围，并且减小增益 当变化量小时，提高锁定精度，而不会在电路配置中扩展位。

    Clock generation apparatus
    7.
    发明申请
    Clock generation apparatus 失效
    时钟发生装置

    公开(公告)号：US20070153126A1

    公开(公告)日：2007-07-05

    申请号：US11712946

    申请日：2007-03-02

    申请人： Hiroshi Sonobe

    发明人： Hiroshi Sonobe

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0994 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/087

    摘要： A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

    摘要翻译： 时钟发生装置设置有频率相位误差计算电路120，由此可以由DTO121基于DTO 10的频率信息和相位误差信息同时产生与脉冲串锁定和线路锁定时钟同步的时钟， 相位比较器7和数字LPF 8。 因此，时钟生成装置能够应付需要多个时钟的系统，通过频率扩展信息生成电路90生成扩展信息容易地进行频率扩展，并且将其添加到DTO 121中。 结果，可以减少从时钟到视频终端的干扰，并且可以利用诸如电视接收机的视频终端的性能。

    Clock generation apparatus
    8.
    发明申请
    Clock generation apparatus 审中-公开

    公开(公告)号：US20060077297A1

    公开(公告)日：2006-04-13

    申请号：US11248254

    申请日：2005-10-13

    申请人： Hiroshi Sonobe

    发明人： Hiroshi Sonobe

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0994 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/087

    摘要： A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

    Semiconductor device for clock signals synchronization accuracy
    9.
    发明授权
    Semiconductor device for clock signals synchronization accuracy 有权
    半导体器件用于时钟信号同步精度

    公开(公告)号：US06819153B2

    公开(公告)日：2004-11-16

    申请号：US10108007

    申请日：2002-03-27

    申请人： Hiroshi Sonobe

    发明人： Hiroshi Sonobe

    IPC分类号： H03L706

    CPC分类号： H04N5/126 ,  H03L7/081

    摘要： A semiconductor device that generates a clock which is synchronized with a reference signal stably and with fixed synchronization accuracy, and enables to deal with an abrupt variation in the reference signal. This semiconductor device includes N stages of delay elements each delaying an external clock by 1/N clock (N: an integer that is two or larger); a phase comparator for comparing the phase of a clock that has been delayed by the N stages of the delay elements with the phase of the external clock one clock late; a controller that receives a phase difference detected by the phase comparator and controls respective delays of the delay elements; and a selector for selecting a delayed clock having the closest phase to the reference signal from delayed clocks which are generated by the N stages of the delay elements, respectively, and shifted in phase with each other by 1/N clock.

    摘要翻译： 一种半导体器件，其以稳定的同步精度生成与参考信号同步的时钟，能够应对基准信号的突变。 该半导体器件包括N级延迟元件，每个延迟元件将外部时钟延迟1 / N时钟（N：两个或更大的整数）; 相位比较器，用于将延迟了N级的延迟元件的时钟的相位与外部时钟的相位相比较迟一个时钟; 控制器，其接收由所述相位比较器检测的相位差并控制所述延迟元件的各个延迟; 以及选择器，用于分别从延迟元件的N级产生的延迟时钟中选择与参考信号最接近的相位的延迟时钟，并相移1 / N个时钟。

    Method of manufacturing solar cell panel
    10.
    发明授权
    Method of manufacturing solar cell panel 失效
    制造太阳能电池板的方法

    公开(公告)号：US07906365B2

    公开(公告)日：2011-03-15

    申请号：US11848976

    申请日：2007-08-31

    申请人： Hiroshi Sonobe ,  Akemi Takano ,  Yoshikazu Nawata ,  Kazumasa Uchihashi ,  Kazuhiko Ogawa ,  Tsukasa Yamane ,  Nobuki Yamashita

    发明人： Hiroshi Sonobe ,  Akemi Takano ,  Yoshikazu Nawata ,  Kazumasa Uchihashi ,  Kazuhiko Ogawa ,  Tsukasa Yamane ,  Nobuki Yamashita

    IPC分类号： H01L21/00 ,  H01L27/142

    CPC分类号： H01L31/186 ,  H01L31/046 ,  H02S50/00 ,  H02S50/15 ,  Y02E10/50 ,  Y02P70/521

    摘要： A method of manufacturing a solar cell panel, includes steps (a) to (e). The step (a) is a step of forming a solar cell module by laminating solar cell films on a transparency substrate. The step (b) is a step of performing an inspection of electric power generation on the solar cell module. The step (c) is a step of forming a solar cell panel by executing a panel formation on the solar cell module. The step (d) is a step of cleaning a light incidence surface of the solar cell panel. The step (e) is a step of performing an inspection of electric power generation on the solar cell panel. The step (d) is executed immediately before the step (e).

    摘要翻译： 一种制造太阳能电池面板的方法，包括步骤（a）至（e）。 步骤（a）是通过在透明基板上层叠太阳能电池膜来形成太阳能电池模块的步骤。 步骤（b）是对太阳能电池模块进行发电检查的步骤。 步骤（c）是通过在太阳能电池模块上执行面板形成来形成太阳能电池面板的步骤。 步骤（d）是清洁太阳能电池面板的光入射面的工序。 步骤（e）是对太阳能电池面板进行发电检查的步骤。 步骤（d）在步骤（e）之前执行。