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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE
    1.
    发明授权
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE 失效
    制造双门结构半导体器件的方法以及制造的半导体器件，其中包括形成具有较低电阻的N型和P型覆层的覆盖区域

    公开(公告)号：US06620666B2

    公开(公告)日：2003-09-16

    申请号：US09766844

    申请日：2001-01-23

    申请人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    发明人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    IPC分类号： H01L21337

    CPC分类号： H01L21/823842

    摘要： There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

    摘要翻译： 描述了制造双栅极结构的半导体器件的方法，该方法防止在双栅极结构的栅电极中发生高电阻局部区域。 在隔离氧化膜上形成要成为双栅极结构的栅电极的导电层的多晶硅层。 将N型杂质注入到多晶硅膜的n型注入区域中，同时将光致抗蚀剂膜作为掩模。 将P型杂质注入多晶硅膜3的p型杂质区，同时将另一种光致抗蚀剂膜作为掩模。 进行n型杂质的注入和p型杂质的注入，使得不可避免地形成以这些重叠的方式掺杂这些杂质的重叠区域。

    Semiconductor device having a dummy pattern
    2.
    发明授权
    Semiconductor device having a dummy pattern 失效
    具有虚拟图案的半导体器件

    公开(公告)号：US06486558B2

    公开(公告)日：2002-11-26

    申请号：US09767134

    申请日：2001-01-23

    申请人： Masao Sugiyama ,  Kenji Yoshiyama

    发明人： Masao Sugiyama ,  Kenji Yoshiyama

    IPC分类号： H01L2348

    CPC分类号： H01L23/522 ,  H01L21/823892 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

    摘要翻译： 描述具有包括多个存储单元的存储单元区域的半导体器件，并且向设置在存储单元块中的所有存储单元赋予稳定特性。 杂质以预定间隔注入到硅衬底的存储单元区域中，从而形成多个阱。 用作植入杂质的掩模的抗蚀剂膜具有带状图案和宽图案。 由于位于靠近宽图案的带状图案倾斜，所以位于存储单元区域的外周附近的孔的特性变得不稳定。 将不稳定特性的阱作为不影响半导体器件功能的虚拟阱。

    Layout of well contacts and source contacts of a semiconductor device
    3.
    发明授权
    Layout of well contacts and source contacts of a semiconductor device 有权
    半导体器件的阱触点和源触点的布局

    公开(公告)号：US6064099A

    公开(公告)日：2000-05-16

    申请号：US285044

    申请日：1999-04-01

    申请人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

    发明人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/74 ,  H01L23/485 ,  H01L29/417 ,  H01L29/41

    CPC分类号： H01L29/66636 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41766 ,  H01L2924/0002

    摘要： There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate region of an NMOS transistor. Further, there are formed a first contact plug to be electrically connected to the n-type source region and a second contact plug to be electrically connected to the n-type drain region. The n-type source region is provided so as to become short-circuited with the p-well. The n-type drain region is provided so as not to become short-circuited with the p-well. The n-type source region is formed so as to become smaller than the n-type drain region.

    摘要翻译： 描述了一种旨在增加晶体管集成度而不损害所需元件特性的半导体器件。 在作为NMOS晶体管的基板区域的p阱中形成n型源极区域和n型漏极区域。 此外，形成电连接到n型源极区域的第一接触插塞和与n型漏极区域电连接的第二接触插塞。 n型源极区域被设置为与p阱短路。 设置n型漏极区以不与p阱短路。 n型源极区域形成为小于n型漏极区域。

    Semiconductor device having a capacitor element
    4.
    发明授权
    Semiconductor device having a capacitor element 失效
    具有电容器元件的半导体器件

    公开(公告)号：US06614643B1

    公开(公告)日：2003-09-02

    申请号：US10286911

    申请日：2002-11-04

    申请人： Kiyoaki Morita ,  Kenji Yoshiyama

    发明人： Kiyoaki Morita ,  Kenji Yoshiyama

    IPC分类号： H01G4228

    CPC分类号： H01L28/57 ,  H01L21/76895 ,  H01L28/40

    摘要： In an MIM capacitor element, a leak guard that covers an upper layer electrode layer is provided between upper layer electrode layer and a reflection prevention film and, therefore, a region is not formed wherein upper layer electrode layer and reflection prevention film make a direct contact with each other. As a result, it becomes possible to completely prevent the generation of a leak current between upper layer electrode layer and reflection prevention film. Thus, an improvement in the structure of the MIM capacitor element and an improvement in a manufacturing process for the same can be achieved, thereby it becomes possible to provide a semiconductor device wherein the reliability of the MIM capacitor element can be enhanced.

    摘要翻译： 在MIM电容元件中，覆盖上层电极层的防漏罩设置在上层电极层和防反射膜之间，因此不形成上层电极层和防反射膜直接接触的区域 与彼此。 结果，可以完全防止上层电极层和防反射膜之间的漏电流的产生。 因此，可以实现MIM电容器元件的结构的改进和其制造工艺的改进，从而可以提供可以提高MIM电容器元件的可靠性的半导体器件。

    Semiconductor device with self-aligned contact structure
    7.
    发明授权
    Semiconductor device with self-aligned contact structure 失效
    具有自对准接触结构的半导体器件

    公开(公告)号：US06479873B1

    公开(公告)日：2002-11-12

    申请号：US09444848

    申请日：1999-11-22

    申请人： Kenji Yoshiyama ,  Keiichi Higashitani

    发明人： Kenji Yoshiyama ,  Keiichi Higashitani

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/28518

    摘要： A semiconductor device more reduced in size and a manufacturing method thereof are provided. A gate electrode is covered with a silicon nitride film having a selecting ratio greater than an NSG film under a prescribed etching condition. A cobalt suicide film is formed on an upper surface of source/drain regions. Furthermore, a refractory metal silicide film forming the gate electrode is formed by a cobalt silicide film.

    摘要翻译： 提供了一种尺寸更小的半导体器件及其制造方法。 在规定的蚀刻条件下，用选择比大于NSG膜的氮化硅膜覆盖栅电极。 在源/漏区的上表面上形成硅化硅膜。 此外，通过硅化钴膜形成形成栅电极的难熔金属硅化物膜。

    Semiconductor device with MIM capacitance element
    8.
    发明授权
    Semiconductor device with MIM capacitance element 有权
    具有MIM电容元件的半导体器件

    公开(公告)号：US06657247B2

    公开(公告)日：2003-12-02

    申请号：US09986578

    申请日：2001-11-09

    申请人： Kenji Yoshiyama ,  Kiyoaki Morita

    发明人： Kenji Yoshiyama ,  Kiyoaki Morita

    IPC分类号： H01L27108

    CPC分类号： H01L28/55 ,  H01L21/76838 ,  H01L23/5222 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A lower metal layer is provided on a lower interlayer insulating film in an MIM capacitance element forming region. The lower metal layer is formed by the same step as that in which the lower interconnection layer is formed. A dielectric layer and an upper metal layer patterned using the same mask are provided on the lower metal layer. The upper metal layer is formed to have a thickness that is thinner than the thickness of the lower metal layer. Thus, it becomes possible to achieve high reliability (lifetime) of the MIM capacitance element by improving the structure of the MIM capacitance element as well as the manufacturing steps.

    摘要翻译： 在MIM电容元件形成区域中的下层间绝缘膜上设置有下层金属层。 下部金属层通过与形成下部互连层的步骤相同的步骤形成。 在下金属层上设置介电层和使用相同掩模图案化的上金属层。 上金属层形成为具有比下金属层的厚度薄的厚度。 因此，通过改善MIM电容元件的结构以及制造步骤，可以实现MIM电容元件的高可靠性（寿命）。