公开(公告)号：US08502300B2

公开(公告)日：2013-08-06

申请号：US13232492

申请日：2011-09-14

申请人： Ryo Fukuda ,  Yoshihisa Iwata

发明人： Ryo Fukuda ,  Yoshihisa Iwata

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  G11C16/0416 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

摘要翻译： 在半导体衬底上方形成绝缘膜。 在电介质膜中形成第一导电层并沿第一方向延伸。 第一导电层连接到第一选择晶体管。 形成在电介质膜中并沿第一方向延伸的第二导电层。 第二导电层连接到第二选择晶体管。 半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。 在半导体层上形成栅极绝缘膜。 栅极绝缘膜包括作为其一部分的电荷累积膜。 第三导电层被栅极绝缘膜包围。

公开(公告)号：US20120068256A1

公开(公告)日：2012-03-22

申请号：US13232492

申请日：2011-09-14

申请人： Ryo Fukuda ,  Yoshihisa Iwata

发明人： Ryo Fukuda ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0416 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

摘要翻译： 在半导体衬底上方形成绝缘膜。 第一导电层形成在电介质膜中并沿第一方向延伸。 第一导电层连接到第一选择晶体管。 形成在电介质膜中并沿第一方向延伸的第二导电层。 第二导电层连接到第二选择晶体管。 半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。 在半导体层上形成栅极绝缘膜。 栅极绝缘膜包括作为其一部分的电荷累积膜。 第三导电层被栅极绝缘膜包围。

公开(公告)号：US08817538B2

公开(公告)日：2014-08-26

申请号：US13493370

申请日：2012-06-11

申请人： Kiyotaro Itagaki ,  Kunihiro Yamada ,  Yoshihisa Iwata

发明人： Kiyotaro Itagaki ,  Kunihiro Yamada ,  Yoshihisa Iwata

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C2213/71 ,  H01L27/11582 ,  H01L29/7926

摘要： A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

摘要翻译： 控制电路被配置为将连接到所选择的存储器串的漏极侧选择晶体管和源极侧选择晶体管设置为非导通状态。 控制电路被配置为对连接到所选择的存储器串中未选择的存储器单元的栅极的未选择字线施加第一电压。 控制电路被配置为对连接到所选择的存储器串中所选择的存储器单元的栅极的选定字线施加第二电压。 在擦除操作中第二电压小于第一电压。

公开(公告)号：US08605508B2

公开(公告)日：2013-12-10

申请号：US13463889

申请日：2012-05-04

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US08169826B2

公开(公告)日：2012-05-01

申请号：US12726858

申请日：2010-03-18

申请人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L29/66

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  G11C16/0483 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

摘要翻译： 非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。 开关电路控制第二线和第一线之间的电连接。

公开(公告)号：US20110096590A1

公开(公告)日：2011-04-28

申请号：US12746866

申请日：2008-09-09

申请人： Yoshihisa Iwata

发明人： Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C11/5614 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a cell array having plural memory cells arranged in matrix, each memory cell including a variable resistor having a resistance reversibly variable to store data corresponding to the resistance of the variable resistor; a selection circuit operative to select a memory cell from the cell array; and a write circuit operative to execute certain voltage or current supply to the memory cell selected by the selection circuit to vary the resistance of a variable resistor in the selected memory cell to erase or write data. The write circuit terminates the voltage or current supply to the selected memory cell in accordance with resistance variation situation of the variable resistor in the selected memory cell when current flowing in the selected memory cell reaches a certain level appeared after the data erase or write.

摘要翻译： 非易失性半导体存储器件包括具有以矩阵形式排列的多个存储单元的单元阵列，每个存储单元包括具有可逆可变电阻的可变电阻器，用于存储对应于可变电阻器的电阻的数据; 选择电路，用于从所述单元阵列中选择存储单元; 以及写入电路，用于对由选择电路选择的存储器单元执行一定的电压或电流供应，以改变所选择的存储器单元中的可变电阻器的电阻以擦除或写入数据。 当电流在所选存储单元中流动的电流达到数据擦除或写入之后出现的一定水平时，写入电路根据所选存储单元中的可变电阻器的电阻变化情况，终止对所选存储单元的电压或电流供应。

公开(公告)号：US20100067283A1

公开(公告)日：2010-03-18

申请号：US12624103

申请日：2009-11-23

申请人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

发明人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

IPC分类号： G11C7/08 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C16/0491 ,  G11C16/26 ,  G11C17/126 ,  G11C2207/002 ,  G11C2207/063

摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

摘要翻译： 根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。 第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。 第六FET的漏极连接到第二输入节点，其源极连接到电源节点。 通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点对第二输出节点充电来启动感测操作。 开始感测操作后，第五和第六FET导通。

公开(公告)号：US20080130176A1

公开(公告)日：2008-06-05

申请号：US12019657

申请日：2008-01-25

申请人： Tadashi KAI ,  Masahiko Nakayama ,  Sumio Ikegawa ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

发明人： Tadashi KAI ,  Masahiko Nakayama ,  Sumio Ikegawa ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

IPC分类号： G11B5/33

CPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/222

摘要： A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including a rectangular part, a first projected part, and a second projected part. The rectangular part has mutually facing first and second longer sides and mutually facing first and second shorter sides. The first projected part projects from the first longer side at a position shifted from the center toward the first shorter side. The second projected part projects from the second longer side at a position shifted from the center toward the second shorter side.

摘要翻译： 磁阻效应元件包括具有相互面对的第一和第二表面的非磁性层。 参考层设置在第一表面上并具有固定的磁化方向。 磁化变化层设置在第二表面上，具有可变的磁化方向，并且具有包括矩形部分，第一突出部分和第二突出部分的平面形状。 矩形部分具有相互面对的第一和第二长边以及相互面对的第一和第二短边。 第一突出部从第一长边突出的位置从中心向第一短边移动。 第二突出部从第二长边突出的位置从中心向第二短边移动。

公开(公告)号：US20060274573A1

公开(公告)日：2006-12-07

申请号：US11194534

申请日：2005-08-02

申请人： Yoshihisa Iwata

发明人： Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic random access memory includes a first magnetoresistive element which is used as a memory element, and a second magnetoresistive element which is used as a current load of a read bias circuit.

摘要翻译： 磁性随机存取存储器包括用作存储元件的第一磁阻元件和用作读偏置电路的电流负载的第二磁阻元件。

公开(公告)号：US07142447B2

公开(公告)日：2006-11-28

申请号：US11133383

申请日：2005-05-20

申请人： Yoshihiro Ueda ,  Yoshihisa Iwata

发明人： Yoshihiro Ueda ,  Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic memory device includes a plurality of variable resistance elements arranged in parallel between a first and second nodes and having resistance values which vary depending on data stored in the elements, a selection transistor connected to the first node to perform selection on the plurality of variable resistance elements, and a bit line connected to the second node. A plurality of current paths including the variable resistance elements between the first and second nodes have different resistance values.

摘要翻译： 一种磁存储器件包括多个可变电阻元件，它们并联布置在第一和第二节点之间，并具有根据存储在元件中的数据而变化的电阻值;连接到第一节点的选择晶体管，以对多个变量进行选择 电阻元件和连接到第二节点的位线。 包括第一和第二节点之间的可变电阻元件的多个电流路径具有不同的电阻值。