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公开(公告)号：US20100127768A1
公开(公告)日：2010-05-27
申请号：US12683171
申请日：2010-01-06
申请人： MIHIRO NONOYAMA , Masataka Kazuno
发明人： MIHIRO NONOYAMA , Masataka Kazuno
IPC分类号： H01L25/00
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side.
摘要翻译： 半导体器件包括第一半导体芯片和第二半导体芯片，其包括高速串行I / F电路，该高速串行I / F电路通过串行总线在高速串行I / F电路和外部设备之间传送串行数据并被堆叠 在第一个半导体芯片上。 沿着短边的第二半导体芯片的第一侧设置有用于连接外部设备和高速串行I / F电路的焊盘（电极）的焊盘区域。 沿着作为长边的第二半导体芯片的第二侧设置有用于连接包括在第一半导体芯片中的内部电路的焊盘和高速串行I / F电路的焊盘区域。
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公开(公告)号：US07668989B2
公开(公告)日：2010-02-23
申请号：US11483556
申请日：2006-07-11
申请人： Mihiro Nonoyama , Masataka Kazuno
发明人： Mihiro Nonoyama , Masataka Kazuno
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side.
摘要翻译： 半导体器件包括第一半导体芯片和第二半导体芯片，其包括高速串行I / F电路，该高速串行I / F电路通过串行总线在高速串行I / F电路和外部设备之间传送串行数据并被堆叠 在第一个半导体芯片上。 沿着短边的第二半导体芯片的第一侧设置有用于连接外部设备和高速串行I / F电路的焊盘（电极）的焊盘区域。 沿着作为长边的第二半导体芯片的第二侧设置有用于连接包括在第一半导体芯片中的内部电路的焊盘和高速串行I / F电路的焊盘区域。
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公开(公告)号：US06639441B2
公开(公告)日：2003-10-28
申请号：US10046186
申请日：2002-01-16
申请人： Masaaki Ono , Masataka Kazuno , Narito Matsuno
发明人： Masaaki Ono , Masataka Kazuno , Narito Matsuno
IPC分类号： H03K3017
CPC分类号： H03K5/1534 , H03K5/133 , H03K5/1565 , H03K5/159
摘要： A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.
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公开(公告)号：US20070028012A1
公开(公告)日：2007-02-01
申请号：US11483538
申请日：2006-07-11
申请人： Mihiro Nonoyama , Masataka Kazuno
发明人： Mihiro Nonoyama , Masataka Kazuno
IPC分类号： G06F13/00
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus, and transfers parallel data between the high-speed serial I/F circuit and an internal circuit included in the first semiconductor chip. A physical layer circuit of the high-speed serial I/F circuit is disposed on a first side of the second semiconductor chip which is the short side, and a logic circuit is disposed on a third side opposite to the first side.
摘要翻译： 半导体器件包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 第二个半导体芯片包括一个高速串行I / F电路，它通过串行总线在高速串行I / F电路和外部设备之间传送串行数据，并在高速串行I / F 电路和包括在第一半导体芯片中的内部电路。 高速串行I / F电路的物理层电路设置在作为短边的第二半导体芯片的第一侧，并且逻辑电路设置在与第一侧相对的第三侧。
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公开(公告)号：US07664895B2
公开(公告)日：2010-02-16
申请号：US11483538
申请日：2006-07-11
申请人： Mihiro Nonoyama , Masataka Kazuno
发明人： Mihiro Nonoyama , Masataka Kazuno
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus, and transfers parallel data between the high-speed serial I/F circuit and an internal circuit included in the first semiconductor chip. A physical layer circuit of the high-speed serial I/F circuit is disposed on a first side of the second semiconductor chip which is the short side, and a logic circuit is disposed on a third side opposite to the first side.
摘要翻译： 半导体器件包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 第二个半导体芯片包括一个高速串行I / F电路，它通过串行总线在高速串行I / F电路和外部设备之间传送串行数据，并在高速串行I / F 电路和包括在第一半导体芯片中的内部电路。 高速串行I / F电路的物理层电路设置在作为短边的第二半导体芯片的第一侧，并且逻辑电路设置在与第一侧相对的第三侧。
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公开(公告)号：US20070028013A1
公开(公告)日：2007-02-01
申请号：US11483556
申请日：2006-07-11
申请人： Mihiro Nonoyama , Masataka Kazuno
发明人： Mihiro Nonoyama , Masataka Kazuno
IPC分类号： G06F13/00
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side.
摘要翻译： 半导体器件包括第一半导体芯片和第二半导体芯片，其包括高速串行I / F电路，该高速串行I / F电路通过串行总线在高速串行I / F电路和外部设备之间传送串行数据并被堆叠 在第一个半导体芯片上。 沿着短边的第二半导体芯片的第一侧设置有用于连接外部设备和高速串行I / F电路的焊盘（电极）的焊盘区域。 沿着作为长边的第二半导体芯片的第二侧设置有用于连接包括在第一半导体芯片中的内部电路的焊盘和高速串行I / F电路的焊盘区域。
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公开(公告)号：US6023157A
公开(公告)日：2000-02-08
申请号：US989772
申请日：1997-12-12
申请人： Masataka Kazuno
发明人： Masataka Kazuno
摘要： According to the present invention, a first voltage is generated at a drain of a first MESFET by a first stage circuit that includes a plurality of diode elements and the first MESFET with its gate and drain connected together provided between power sources. The first voltage is applied to a gate of a second MESFET that performs a source follower operation so that a constant second voltage, which is lower by the equivalent of a threshold voltage than the first voltage, is generated at the source. A third MESFET with a diode connection is provided between the second voltage source and a lower power source, and a bias voltage is generated at the drain terminal of the third MESFET. The bias voltage is supplied to the gate of a constant-current transistor, the source of which is connected to the lower power source. The current of the constant-current transistor is supplied to an SCFL circuit, the source of which is connected for common use.
摘要翻译： 根据本发明，在包括多个二极管元件的第一级电路的第一MESFET的漏极处产生第一电压，并且在电源之间连接有第一MESFET的栅极和漏极连接在一起。 第一电压被施加到执行源极跟随器操作的第二MESFET的栅极，使得在源极处产生比等于第一电压的阈值电压相当的恒定的第二电压。 在第二电压源和下电源之间提供具有二极管连接的第三MESFET，并且在第三MESFET的漏极端产生偏置电压。 偏置电压被提供给恒流晶体管的栅极，其源极连接到下电源。 恒流晶体管的电流被提供给SCFL电路，SCFL电路的源极连接用于常用。
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公开(公告)号：US08611165B2
公开(公告)日：2013-12-17
申请号：US13334321
申请日：2011-12-22
申请人： Masataka Kazuno
发明人： Masataka Kazuno
IPC分类号： G11C7/00
CPC分类号： G11C29/026 , G11C29/36 , G11C29/38 , G11C29/44
摘要： A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell.
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9.发明授权公开(公告)号：US08296642B2
公开(公告)日：2012-10-23
申请号：US12725744
申请日：2010-03-17
申请人： Masataka Kazuno , Kiminori Nakajima
发明人： Masataka Kazuno , Kiminori Nakajima
IPC分类号： G06F11/00
CPC分类号： H03K19/23
摘要： A signal judgement circuit making a judgement on a signal includes: an error signal generation circuit receiving signals via at least four signal lines and outputting an error signal when, of all the received signals, the number of signals taking on a same value does not exceed half of the number of the received signals; and an output selection circuit selecting any one of the received signals and outputting the selected signal.
摘要翻译： 对信号进行判断的信号判断电路包括：误差信号生成电路，经由至少四条信号线接收信号，并输出误差信号，当接收到的所有信号的信号数量相同值不超过 接收信号数量的一半; 以及输出选择电路，选择接收信号中的任何一个并输出所选择的信号。
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公开(公告)号：US08001301B2
公开(公告)日：2011-08-16
申请号：US12683171
申请日：2010-01-06
申请人： Mihiro Nonoyama , Masataka Kazuno
发明人： Mihiro Nonoyama , Masataka Kazuno
CPC分类号： G06F13/4072 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side.
摘要翻译： 半导体器件包括第一半导体芯片和第二半导体芯片，其包括高速串行I / F电路，该高速串行I / F电路通过串行总线在高速串行I / F电路和外部设备之间传送串行数据并被堆叠 在第一个半导体芯片上。 沿着短边的第二半导体芯片的第一侧设置有用于连接外部设备和高速串行I / F电路的焊盘（电极）的焊盘区域。 沿着作为长边的第二半导体芯片的第二侧设置有用于连接包括在第一半导体芯片中的内部电路的焊盘和高速串行I / F电路的焊盘区域。
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