公开(公告)号：US5278459A

公开(公告)日：1994-01-11

申请号：US791695

申请日：1991-11-14

申请人： Masataka Matsui ,  Kiyofumi Ochii ,  Katsuhiko Sato

发明人： Masataka Matsui ,  Kiyofumi Ochii ,  Katsuhiko Sato

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H03K3/356

CPC分类号： H03K3/356052 ,  G11C11/412 ,  H01L27/1108 ,  Y10S257/903

摘要： According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first TFT is connected to the second memory node, and a gate of the second TFT is connected to the first data storage node, such that a flip-flip circuit is formed by the first power supply terminal, the second power supply terminal, the first TFT, the second TFT, the third TFT, and the fourth TFT, and further including data bit lines which are inverted with respect to each other, a first switching device for performing a switching operation between one of the bit lines and the first data storage node, a second switching device for performing a switching operation between the other of the data bit lines and the second data memory, and a word line device, connected to gates of the first and second switching devices, for controlling operations of the first and second switching devices.

摘要翻译： 根据本发明，提供了一种半导体静态数据存储装置，包括：第一电源端子，第二电源端子，第一TFT（薄膜晶体管），第一TFT，具有第一导电类型，一个端子连接到 第一电源端子和连接到用于存储第二数据的第一数据存储节点的另一终端，第二TFT，具有第一导电类型的TFT，连接到第一电源端子的一个端子，以及连接到第一电源端子的另一个端子 到第二数据存储节点，用于存储数据，第三TFT，具有第二导电类型的第三TFT，连接到第二电源端的一个端子和连接到第一数据存储节点的另一个端子;以及第四TFT ，具有第二导电类型的第四TFT，一个端子连接到第二电源端子，另一个端子连接到第二数据存储节点，其中 在第一TFT的栅极连接到第二存储器节点，并且第二TFT的栅极连接到第一数据存储节点，使得由第一电源端子形成翻盖电路，第二电源 供电端子，第一TFT，第二TFT，第三TFT和第四TFT，并且还包括彼此相反的数据位线;第一开关器件，用于在位线之间执行切换操作 和第一数据存储节点，用于执行另一数据位线和第二数据存储器之间的切换操作的第二切换装置，以及连接到第一和第二开关装置的栅极的字线装置，用于控制操作 的第一和第二开关装置。

公开(公告)号：US5276647A

公开(公告)日：1994-01-04

申请号：US813438

申请日：1991-12-26

申请人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

IPC分类号： G11C11/413 ,  G01R31/28 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C8/12 ,  G11C11/41

摘要： SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

摘要翻译： SRAM包括字线驱动电路，其根据正常操作时的输入地址选择预定数量的字线，并且同时选择大于所选择的字线数量的所有字线或字线 在正常工作时，在电压应力测试时，以及在正常工作时向所述一对位线施加预定偏置电压的位线负载电路，并且将偏置电压控制为不 施加到所述一对位线中的至少一个或在电压应力测试时施加低于正常操作时的偏置电压的偏置电压。

公开(公告)号：US5239501A

公开(公告)日：1993-08-24

申请号：US735047

申请日：1991-07-24

申请人： Masataka Matsui ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Kiyofumi Ochii

IPC分类号： G11C11/41

CPC分类号： G11C11/41

摘要： In a static memory, a memory cell is constituted by only the same-channel MOSFETs. With the MOSFETs of the same channel, no well isolation region is required, and a cell size can be decreased. Moreover, the high potential side power source of a flip-flop can be used as a read word line. Thus the read word line can be driven by an ECL logic circuit.

摘要翻译： 在静态存储器中，存储单元仅由相同通道的MOSFET构成。 使用相同通道的MOSFET，不需要良好的隔离区域，并且可以减小单元尺寸。 此外，触发器的高电位侧电源可以用作读字线。 因此，读取字线可以由ECL逻辑电路驱动。

公开(公告)号：US4958316A

公开(公告)日：1990-09-18

申请号：US288199

申请日：1988-12-22

申请人： Kiyofumi Ochii ,  Masataka Matsui ,  Osamu Ozawa

发明人： Kiyofumi Ochii ,  Masataka Matsui ,  Osamu Ozawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/412 ,  G11C29/00 ,  G11C29/50 ,  H01L27/11

CPC分类号： G11C11/412 ,  G11C5/146 ,  H01L27/1112

摘要： A static random access memory comprising a semiconductor substrate, a well region formed in the substrate and containing at least one memory cell, and a power-supply terminal connected to the well region, for applying a given bias voltage to the well region.

摘要翻译： 一种静态随机存取存储器，包括半导体衬底，形成在衬底中并包含至少一个存储单元的阱区，以及连接到阱区的电源端，用于向阱区施加给定的偏置电压。

公开(公告)号：US4901284A

公开(公告)日：1990-02-13

申请号：US288198

申请日：1988-12-22

申请人： Kiyofumi Ochii ,  Masataka Matsui ,  Osamu Ozawa

发明人： Kiyofumi Ochii ,  Masataka Matsui ,  Osamu Ozawa

IPC分类号： G11C11/413 ,  G11C11/412 ,  G11C29/00 ,  G11C29/50 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C11/412

摘要： A static random access memory comprising a memory cell array, a plurality of peripheral circuits, first and second power-supply voltage lines, a bonding pad, and a level-shifting circuit. The array has static memory cells each having resistors functioning as load elements. The peripheral circuits control the writing of data into, and the reading of data from, the static memory cells. The first power-supply voltage line applies a first power-supply voltage to the peripheral circuits. The bonding pad is connected to the first power-supply voltage line. The second power-supply voltage line applies a second power-supply voltage to the static memory cells. The level-shifting means is connected between the first and second power-supply voltage lines, for shifting the level of the first power-supply voltage and applying the level-shifted voltage to the static memory cells via said second power-supply voltage line.

摘要翻译： 一种包括存储单元阵列，多个外围电路，第一和第二电源电压线，接合焊盘和电平移动电路的静态随机存取存储器。 该阵列具有各自具有用作负载元件的电阻的静态存储单元。 外围电路控制将数据写入静态存储单元的数据和读取数据。 第一电源电压线向外围电路施加第一电源电压。 接合焊盘连接到第一电源电压线。 第二电源电压线将静态存储单元施加第二电源电压。 电平移动装置连接在第一和第二电源电压线之间，用于移动第一电源电压的电平，并经由所述第二电源电压线将电平移位的电压施加到静态存储单元。

公开(公告)号：US5091889A

公开(公告)日：1992-02-25

申请号：US456452

申请日：1989-12-26

申请人： Takahiro Hamano ,  Masataka Matsui ,  Katsuhiko Sato

发明人： Takahiro Hamano ,  Masataka Matsui ,  Katsuhiko Sato

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C11/409 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C7/22 ,  G11C11/418 ,  G11C11/419

摘要： An address transition detecting circuit detects on address transition signal generated during the writing of input data into a static random access memory (SRAM) and generates an address detection signal as a monostable pulse of a predetermined length. A bit line precharge and equalize signals generating circuit generates, in synchronization with the address transition detection signal and an input signal on a write data line, a bit line precharge signal and bit line equalize signal which are supplied to their columns in memory. At a time of reading, the bit line precharge and equalize signals generating circuit supplies a high level potential to paired data lines to prevent a data entry from being made into the paired write data lines by a resetting operation. At a time of writing, a write data buffer circuit supplies complementary data to the paired write data lines and prevents a data signal entry from being made by a presetting operation onto the paired write data lines, for a predetermined period of time, in synchronization with the address transition detection signal. It is, therefore, possible to prevent an input signal entry for a predetermined period of time by a resetting operation and hence prevent a write error.

摘要翻译： 地址转换检测电路检测在将输入数据写入静态随机存取存储器（SRAM）期间产生的地址转换信号，并产生作为预定长度的单稳态脉冲的地址检测信号。 位线预充电和均衡信号产生电路与地址转换检测信号和写数据线上的输入信号同步地产生在存储器中提供给它们的列的位线预充电信号和位线均衡信号。 在读取时，位线预充电和均衡信号发生电路向成对数据线提供高电平电位，以防止通过复位操作使数据输入成对的写入数据线。 在写入时，写入数据缓冲电路为配对的写入数据线提供互补的数据，并且防止数据信号进入预设的时间段内的预设操作，与预定的时间段同步 地址转换检测信号。 因此，可以通过复位操作来防止输入信号输入预定的时间段，并且因此防止写入错误。

公开(公告)号：US07487370B2

公开(公告)日：2009-02-03

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。 电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

公开(公告)号：US5399894A

公开(公告)日：1995-03-21

申请号：US23153

申请日：1992-10-28

申请人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

发明人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/737 ,  H01L27/02 ,  H01L29/161

CPC分类号： H01L27/0623 ,  H01L29/7378

摘要： A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

摘要翻译： 本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。 双极晶体管是具有异质结的异质结晶体管。 异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

公开(公告)号：US5357479A

公开(公告)日：1994-10-18

申请号：US693608

申请日：1991-04-30

申请人： Masataka Matsui

发明人： Masataka Matsui

IPC分类号： G11C8/10 ,  G11C8/18 ,  G11C11/407 ,  G11C11/418 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C11/418 ,  G11C8/18

摘要： Memory cell arranged in a matrix configuration are selected by a particular word line to supply the stored data to particular bit lines. The row address decoder selects a particular word line based on the address signal, while the column address decoder selects particular bit lines based on the address signal. Each of the row address decoder and column address decoder contains a first decoder for decoding the address signal, a delay circuit for delaying the output from the first decoder when data is written into the memory cell, and a second decoder for receiving the output signals from the first decoder and delay circuit and based on these signals, selecting either a particular word line or particular bit lines.

摘要翻译： 通过特定字线选择以矩阵配置布置的存储单元，以将存储的数据提供给特定的位线。 行地址解码器基于地址信号选择特定字线，而列地址解码器基于地址信号选择特定的位线。 行地址解码器和列地址解码器中的每一个包含用于解码地址信号的第一解码器，用于当数据被写入存储单元时将来自第一解码器的输出延迟的延迟电路，以及用于从第一解码器接收来自 第一解码器和延迟电路，并且基于这些信号，选择特定字线或特定位线。

公开(公告)号：US4815040A

公开(公告)日：1989-03-21

申请号：US100640

申请日：1987-09-24

申请人： Masataka Matsui ,  Takayuki Ohtani

发明人： Masataka Matsui ,  Takayuki Ohtani

IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419

摘要： In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.

摘要翻译： 在选定的列中，不选择上拉晶体管对，而是选择传输栅极晶体管对。 在读取模式下，传输栅极晶体管对用作位线对之间的上拉负载。 然而，传输栅极晶体管对保持截止，直到位线对上的电压从电源电位电平降低到传输栅极晶体管的阈值电压电平。 因此，当位线对上的电压在等于电源电位电平的电压到低于电源电位的电位的范围内时，在位线对中不形成直流电流路径， 阈值电压电平，并且位线对上的电位差的增加速率由存储单元的引入电流决定。 因此，可以实现高速感测操作。 在写入模式下，传输栅极晶体管对用于位线上拉功能。 由于没有布置正常导通的位线负载晶体管，所以不存在包括位线对的直流电路，因此可以实现低功耗。