公开(公告)号：US08461006B2

公开(公告)日：2013-06-11

申请号：US13434889

申请日：2012-03-30

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

摘要翻译： 可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。 该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第二栅极绝缘膜上形成具有Ni / Si <31/12以上的第一栅极绝缘膜的第一镍硅化物和具有Ni / Si> 31/12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

公开(公告)号：US08168499B2

公开(公告)日：2012-05-01

申请号：US12662581

申请日：2010-04-23

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

摘要翻译： 可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。 该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第一栅极绝缘膜上方形成具有Ni / Si <31/12的组成的第一硅化镍和在所述第二栅极绝缘膜上具有Ni /Si≥31/ 12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

公开(公告)号：US07727832B2

公开(公告)日：2010-06-01

申请号：US11907353

申请日：2007-10-11

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

公开(公告)号：US20100210100A1

公开(公告)日：2010-08-19

申请号：US12662581

申请日：2010-04-23

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

摘要翻译： 可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。 该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第一栅极绝缘膜上方形成具有Ni / Si <31/12的组成的第一硅化镍和在所述第二栅极绝缘膜上具有Ni /Si≥31/ 12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

公开(公告)号：US20080185656A1

公开(公告)日：2008-08-07

申请号：US11907353

申请日：2007-10-11

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

摘要翻译： 可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。 该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第二栅极绝缘膜上形成具有Ni / Si <31/12以上的第一栅极绝缘膜的第一镍硅化物和具有Ni / Si> 31/12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

公开(公告)号：US08404575B2

公开(公告)日：2013-03-26

申请号：US13311850

申请日：2011-12-06

申请人： Akio Kaneko ,  Seiji Inumiya

发明人： Akio Kaneko ,  Seiji Inumiya

IPC分类号： H01L21/3205

CPC分类号： H01L21/31604 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/318 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.

摘要翻译： 本发明的半导体器件包括：半导体层; 设置在所述半导体层上并且包括Hf和Zr中的至少一种的栅极绝缘膜; 以及设置在所述栅极绝缘膜上并包括包含Hf和Zr中的至少一种的碳氮化物的栅电极。

公开(公告)号：US20100003813A1

公开(公告)日：2010-01-07

申请号：US12585334

申请日：2009-09-11

申请人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

IPC分类号： H01L21/28

CPC分类号： C23C16/401 ,  C23C16/56 ,  H01L21/02329 ,  H01L21/3145

摘要： According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：选择性地形成在半导体衬底的预定区域上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及在所述半导体衬底的表面部分中形成在位于所述栅极电极下方的沟道区域的两侧上的源极区和漏极区，其中所述栅极绝缘膜与所述栅电极接触的界面中的碳浓度 不大于5×1022原子/ cm3。

公开(公告)号：US20090114996A1

公开(公告)日：2009-05-07

申请号：US12261770

申请日：2008-10-30

申请人： Seiji Inumiya ,  Takuya Kobayashi ,  Tomonori Aoyama

发明人： Seiji Inumiya ,  Takuya Kobayashi ,  Tomonori Aoyama

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/02148 ,  H01L21/02156 ,  H01L21/02161 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645

摘要： A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate and a first insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film and which has a first element forming electric dipoles that reduce a threshold voltage of the first MISFET and the second MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate, and a second insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film formed on the surface of the substrate and which has a second element forming electric dipoles in a direction opposite to that in the first MISFET.

摘要翻译： 半导体器件包括在其表面上具有第一和第二区域的衬底，在第一区域中形成的第一导电类型的第一MISFET和形成在第二区域中的第二导电类型的第二MISFET。 第一MISFET包括在基板的表面上形成的氧化硅膜或氮氧化硅膜，以及形成为与氧化硅膜或氮氧化硅膜接触形成的第一元件的第一绝缘膜，其具有形成电偶极子的第一元件， 降低第一MISFET的阈值电压，并且第二MISFET包括在衬底的表面上形成的氧化硅膜或氧氮化硅膜，以及形成为与氧化硅膜或氮氧化硅膜接触的第二绝缘膜 形成在基板的表面上，并且具有在与第一MISFET中的方向相反的方向上形成电偶极子的第二元件。

公开(公告)号：US20070235799A1

公开(公告)日：2007-10-11

申请号：US11763070

申请日：2007-06-14

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513

摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。

公开(公告)号：US07091135B2

公开(公告)日：2006-08-15

申请号：US10798337

申请日：2004-03-12

申请人： Seiji Inumiya ,  Kazuhiro Eguchi

发明人： Seiji Inumiya ,  Kazuhiro Eguchi

IPC分类号： H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： There is disclosed a method of manufacturing a semiconductor device, which comprises forming a film containing metal elements and silicon elements on a semiconductor substrate, exposing the semiconductor substrate to an atmosphere containing an oxidant to form a silicon dioxide film at the interface between the semiconductor substrate and the film containing metal elements and silicon elements, and nitriding the film containing metal elements and silicon elements after forming the silicon dioxide film.

摘要翻译： 公开了一种制造半导体器件的方法，其包括在半导体衬底上形成含有金属元素和硅元素的膜，将半导体衬底暴露于含有氧化剂的气氛中，以在半导体衬底之间的界面处形成二氧化硅膜 并且所述膜含有金属元素和硅元素，并且在形成二氧化硅膜之后氮化包含金属元素和硅元素的膜。