公开(公告)号：US08404575B2

公开(公告)日：2013-03-26

申请号：US13311850

申请日：2011-12-06

申请人： Akio Kaneko ,  Seiji Inumiya

发明人： Akio Kaneko ,  Seiji Inumiya

IPC分类号： H01L21/3205

CPC分类号： H01L21/31604 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/318 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.

摘要翻译： 本发明的半导体器件包括：半导体层; 设置在所述半导体层上并且包括Hf和Zr中的至少一种的栅极绝缘膜; 以及设置在所述栅极绝缘膜上并包括包含Hf和Zr中的至少一种的碳氮化物的栅电极。

公开(公告)号：US20100003813A1

公开(公告)日：2010-01-07

申请号：US12585334

申请日：2009-09-11

申请人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

IPC分类号： H01L21/28

CPC分类号： C23C16/401 ,  C23C16/56 ,  H01L21/02329 ,  H01L21/3145

摘要： According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：选择性地形成在半导体衬底的预定区域上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及在所述半导体衬底的表面部分中形成在位于所述栅极电极下方的沟道区域的两侧上的源极区和漏极区，其中所述栅极绝缘膜与所述栅电极接触的界面中的碳浓度 不大于5×1022原子/ cm3。

公开(公告)号：US07968397B2

公开(公告)日：2011-06-28

申请号：US12659250

申请日：2010-03-02

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L21/38

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

公开(公告)号：US07375403B2

公开(公告)日：2008-05-20

申请号：US10738049

申请日：2003-12-18

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物构成的栅极绝缘膜， 或四价金属氧化物和SiON的混合物，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且栅电极 由功能为4eV至5.5eV的金属制成。

公开(公告)号：US20080054378A1

公开(公告)日：2008-03-06

申请号：US11889278

申请日：2007-08-10

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为 主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜 含有SiO 2作为主要成分的Hf，Zr和N.

公开(公告)号：US07141466B2

公开(公告)日：2006-11-28

申请号：US10962673

申请日：2004-10-13

申请人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

发明人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/518 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/78

摘要： According to the present invention, there is provided a semiconductor device comprising:an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer;a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film;a gate electrode formed on said gate insulating film; andsource and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

公开(公告)号：US20060093731A1

公开(公告)日：2006-05-04

申请号：US11260253

申请日：2005-10-28

申请人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

IPC分类号： C23C16/52 ,  H05H1/24 ,  B05C11/00 ,  C23C16/00

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/14

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

公开(公告)号：US20050236678A1

公开(公告)日：2005-10-27

申请号：US10962673

申请日：2004-10-13

申请人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

发明人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L29/518 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/78

摘要： According to the present invention, there is provided a semiconductor device comprising: an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer; a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film; a gate electrode formed on said gate insulating film; and source and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

公开(公告)号：US08039333B2

公开(公告)日：2011-10-18

申请号：US12359974

申请日：2009-01-26

申请人： Akio Kaneko ,  Seiji Inumiya ,  Tomonori Aoyama ,  Takuya Kobayashi

发明人： Akio Kaneko ,  Seiji Inumiya ,  Tomonori Aoyama ,  Takuya Kobayashi

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/823431 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

摘要： A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：在半导体衬底上形成SiGe晶体层，所述SiGe晶体层具有第一平面和相对于第一平面倾斜的第二平面; 在SiGe晶体层上形成非晶Si膜; 通过使用SiGe晶体层的第一和第二平面作为种子进行热处理，使位于非晶Si膜的第一和第二平面附近的部分结晶，从而形成Si晶体层; 通过热处理选择性去除或稀薄未结晶的非晶Si膜的一部分; 对Si晶体层的表面进行氧化处理，从而在Si晶体层的表面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

公开(公告)号：US07687869B2

公开(公告)日：2010-03-30

申请号：US12081824

申请日：2008-04-22

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。